AFE032 datasheet(28/77 Pages) TI1

28 / 77 page

AFE032

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

www.ti.com

The device digital logic sends valid samples to the DAC as long as the external DSP asserts the DAC_MODE pin

and sends 12-bit samples to the device. Note that whenever DAC_MODE is not asserted, whichever values are

present in the output stage of the DSP path continue to be driven to the DAC. Note also that, by default, all

digital processing blocks in the device retain their states when DAC mode is deasserted (see the DSP Path State

Retention section for more details). Use the following sequence to write samples to the DAC:

1. Send a valid XCLK signal to the device (refer to the AFE032 Clock Requirements section for more details on

the XCLK signal).

2. Set CS low.

3. Wait for at least 20 DAC_CLK cycles.

4. Set DAC (pin 7) high. This setting places the device in DAC mode.

5. Write the first 12-bit word to DIN. Note that the DAC register is left-justified.

6. Set CS high to indicate that the sample is entered.

7. Wait for at least four SCLK cycles.

8. Set CS low.

9. Write the subsequent 12-bit word to DIN. Note that the DAC register is left-justified.

10. Set CS high for at least four SCLK cycles to indicate that the sample is entered.

11. Repeat the last three steps for each new DAC sample.

NOTE

The only exception to the 12-bit DAC sample length is when using a 16-bit envelope. See

the SPI Envelope Exception Case section for more details.

Appending 24 mid-range value samples at the end of every transmission of DAC samples is recommended.

These 24 samples provide a smooth transition of the entire transmit path (that is, DSP blocks, Tx PGA, and Tx

filter) to SPI mode. When the transmission of the last DAC sample ends (and the CS pin is set high), wait for at

least 20 DAC_CLK cycles before bringing the DAC pin (pin 7) low.

SPI Envelope Exception Case

Some external processors cannot create a 12-bit wide SPI transmission and output 16 bits. If this limitation is

encountered, the device supports a special mode where a 12-bit DAC sample can be sent over the SPI inside a

16-bit window. To use the AFE032 16-bit SPI envelope feature take into account the following points:

•

Set the DAC SPI select bit (bit 0 of the REG_AFE032_CTRL register) to '1'.

•

Wait for at least 20 DAC_CLK cycles after setting the DAC SPI select bit.

•

Set the DAC pin (pin 7) high. This setting places the device in DAC mode.

•

Drive the 12-bit DAC sample in the MSB position of the 16-bit SPI envelope.

•

Provide 16 valid SCLK cycles in the SPI envelope.

The AFE032 SPI slave latches the first 12 bits and forwards them to the DSP path. The remaining four bits are

dropped. When operating the device with the 16-bit SPI envelope enabled, the SPI must be driven exactly as

described in this section or the device will not process the DAC samples successfully.

Digital Filtering

Blocks 1 and 2 of the DSP path provide digital filtering to the samples generated by the external processor.

This section provides recommendations for the coefficient values for filter block 1 and filter block 2 of the DSP

path. Three frequency bands are considered:

•

CENELEC A band, comprised of frequencies between 3 kHz and 95 kHz.

•

ARIB band, comprised of frequencies between 10 kHz and 450 kHz.

•

FCC band, comprised of frequencies between 10 kHz and 490 kHz.

Note that the addresses of all registers mentioned in this section are given in the REGISTER MAP section.

Table 6 provides the recommended PRE_CLK_DIV and POST_CLK_DIV values of the REG_CLK_DIV register

for the case of a 37.5 MHz XCLK frequency.

Submit Documentation Feedback

Product Folder Links: AFE032

AFE032 датащи(PDF) 28 Page - Texas Instruments

AFE032 датащи(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL