AFE032 datasheet(25/77 Pages) TI1

25 / 77 page

AFE032

www.ti.com

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

DIGITAL LOGIC INTERFACE

The primary functions of the AFE032 digital module are to:

•

Provide an interface for an external DSP to configure the internal blocks of the AFE032.

•

Provide a digital processing path that conditions samples coming from an external DSP.

•

Transmit the conditioned samples to the internal 12-bit DAC.

To accomplish these functions, the device digital logic supports two modes of operation: SPI mode and DAC

mode.

In SPI mode, the device processes commands to either configure the internal analog and digital circuits or to

provide status to an external DSP. In DAC mode, an external DSP uses the SPI to provide DAC samples to the

device.

Descriptions of all the registers mentioned in this section can be found in the Register Map section.

AFE032 Clock Requirements

The device requires the following clocks: XCLK and SCLK.

XCLK is a free-running clock with a 50/50 duty cycle, frequency ranges from 10 MHz to 40 MHz, and less than

180 ps of RMS jitter. SCLK is an SPI clock used for the SPI interface with frequency ranges from 14 MHz to 30

MHz. This clock is active when CS is '0'.

The device contains two programmable clock dividers that can be used to generate the internal DAC clock

(referred to as DAC_CLK). This internal DAC clock determines the rate at which the internal device DAC updates

its analog output. The internal DAC clock is also used by the digital logic in the device (with the exception of the

SPI slave module that requires a separate SCLK signal). The REG_CLK_DIV register is programmed by the user

to control the internal DAC clock frequency. The internal DAC clock is created by two 4-bit clock dividers in

series. Each divider is a 4-bit decimal clock divider that can divide the frequency of the XCLK signal by an

integer between 1 and 16. Each clock divider produces an N+1 divided-down clock, where N is the programmed,

4-bit divide value. The XCLK frequency can be divided by a maximum value of 256. The first divider in the series

is controlled by the POST_CLK_DIV bits (bits 7 to 4 in the REG_CLK_DIV register) and the second divider is

controlled by the PRE_CLK_DIV bits (bits 3 to 0 in the REG_CLK_DIV register). If the application does not need

to divide XCLK by a value greater than 16, then POST_CLK_DIV is not programmed because these bits default

to '0'. For applications where XCLK must be divided down by a number greater than 16, both PRE_CLK_DIV and

POST_CLK_DIV are used to create the target divide-down value required to generate DAC_CLK. In sum, the

relationship between XCLK and DAC_CLK can be expressed as Equation 3:

XCLK = (POST_CLK_DIV + 1) (PRE_CLK_DIV + 1) (DAC_CLK)

(3)

Note that for proper device operation, DAC_CLK must always be slower than SCLK.

In DAC mode, an external processor (also referred to as the SPI master or external DSP) transmits DAC

samples to the device via the SPI at a rate of fS samples per second. fS may be less than or equal to DAC_CLK;

however, the external processor clock and the AFE032 XCLK must be generated from the same crystal.

Power-Up Sequence

A specific power-up sequence must be implemented to properly use the AFE032. The device internal blocks are

disabled if proper VDD levels are not maintained. The following sequence applies at power-up (note that the SD

pin must be held low throughout the entire power-up sequence):

•

Power is applied to the device.

•

When the supply connected to the AVDD1, AVDD2, and DVDD pins reaches a valid, 3-V dc voltage level, the

device digital logic comes out of reset.

•

At this point, a valid XCLK signal is sent to the device for at least 65,536 cycles.

Every time power is applied to the device, in addition to the power-up sequence, a complete initialization

sequence must be followed before the user can transmit data with the power amplifier. The complete initialization

sequence must be followed also after a soft reset is performed (see the AFE032 Reset Options section for more

information on soft reset). The Initialization Sequence section provides more details. Similarly, perform a

sequence each time the device transitions from receiver mode (also referred to as RX mode) to transmitter mode

(also referred to as TX mode). The Power Amplifier Enable Sequence section provides more details for this Rx to

Tx mode transition sequence.

Submit Documentation Feedback

Product Folder Links: AFE032

AFE032 датащи(PDF) 25 Page - Texas Instruments

AFE032 датащи(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL