MSC1202Y2RHHT datasheet(55/92 Pages) TI1

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MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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Auxiliary Interrupt Poll (AIPOL)

Reset Value

SFR A4h

SECIP

SUMIP

ADCIP

MSECIP

I2CIP

CNTIP

ALVDIP

00h

Interrupts are enabled by EICON.4 (SFR D8h). The other interrupts are controlled by the IE and EIE registers.

SECIP

Second System Timer Interrupt Poll (before IRQ masking).

bit 7

0 = Second system timer interrupt poll inactive

1 = Second system timer interrupt poll active

SUMIP

Summation Interrupt Poll (before IRQ masking).

bit 6

0 = Summation interrupt poll inactive

1 = Summation interrupt poll active

ADCIP

ADC Interrupt Poll (before IRQ masking).

bit 5

0 = ADC interrupt poll inactive

1 = ADC interrupt poll active

MSECIP

Millisecond System Timer Interrupt Poll (before IRQ masking).

bit 4

0 = Millisecond system timer interrupt poll inactive

1 = Millisecond system timer interrupt poll active

I2CIP

I2C Start/Stop Interrupt Poll (before IRQ masking).

bit 3

0 = I2C start/stop interrupt poll inactive

1 = I2C start/stop interrupt poll active

CNTIP

Serial Bit Count Interrupt Poll (before IRQ masking).

bit 2

0 = Serial bit count interrupt poll inactive

1 = Serial bit count interrupt poll active

ALVDIP

Analog Low Voltage Detect Interrupt Poll (before IRQ masking).

bit 1

0 = Analog low voltage detect interrupt poll inactive (AVDD > ALVD threshold; ALVD threshold set in LVDCON, E7h)

1 = Analog low voltage detect interrupt poll active (AVDD < ALVD threshold; ALVD threshold set in LVDCON, E7h)

Pending Auxiliary Interrupt (PAI)

Reset Value

SFR A5h

PAI3

PAI2

PAI1

PAI0

00h

PAI

Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the

bits 3−0

appropriate interrupt routine. All of these interrupts vector through address 0033h.

PAI3

PAI2

PAI1

PAI0

AUXILIARY INTERRUPT STATUS

No Pending Auxiliary IRQ.

Reserved.

Analog Low Voltage Detect IRQ and Possible Lower Priority Pending.

I2C IRQ and Possible Lower Priority Pending.

Serial Bit Count Interrupt and Possible Lower Priority Pending.

Millisecond System Timer IRQ and Possible Lower Priority Pending.

ADC IRQ and Possible Lower Priority Pending.

Summation IRQ and Possible Lower Priority Pending.

Second System Timer IRQ.

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