MSC1202Y2RHHT datasheet(32/92 Pages) TI1

32 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

www.ti.com

I2C

The I/O pins needed for I2C transfer are serial clock (SCL)

and serial data (SDA—implemented by connecting DIN

and DOUT externally). The I2C transfer timing is shown in

Figure 19.

The MSC120x I2C supports:

Master or slave I2C operation (control in software)

Standard or fast modes of transfer

Clock stretching

General call

When used in I2C mode, pins DIN (P1.3) and DOUT (P1.2)

should be tied together externally. The DIN pin should be

configured as an input pin and the DOUT pin should be

configured as open drain or standard 8051 by setting the

P1DDR (DOUT should be set high so that the bus is not

pulled low).

The MSC120x I2C can generate two interrupts:

I2C interrupt for START/STOP interrupt (AIE.3)

CNT interrupt for bit counter interrupt (AIE.2)

The START/STOP interrupt is generated when a START

condition or STOP condition is detected on the bus. The bit

counter generates an interrupt on a complete (8-bit) data

transfer and also after the transfer of the ACK/NACK.

The bit counter for serial transfer is always incremented on

the falling edge of SCL and can be reset by reading or

writing to I2CDATA (SFR 9Bh) or when a START/STOP

condition is detected. The bit counter can be polled or used

as an interrupt. The bit counter interrupt occurs when the

bit counter value is equal to 8, indicating that eight bits of

data have been transferred. I2C mode also allows for

interrupt

generation

one

bit

data

transfer

(I2CCON.CNTSEL). This can be used for ACK/NACK

interrupt generation. For instance, the I2C interrupt can be

configured for 8-bit interrupt detection; on the eighth bit,

the interrupt is generated. During this interrupt, the clock

is stretched (SCL held low) if the DCS bit is set. The

interrupt can then be configured for 1-bit detection (which

terminates clock stretching). The ACK/NACK can be

written by the software, which will terminate clock

stretching. The next interrupt will be generated after the

ACK/NACK has been latched by the receiving device. The

interrupt is cleared on reading or writing to the I2CDATA

transfer, the interrupt will be removed and the previous

data will be lost.

Master Operation

The source for the SCL is controlled in the PASEL register

or can be generated in software.

Transmit

The serial data must be stable on the bus while SCL is

high. Therefore, the writing of serial data to I2CDATA must

be coordinated with the generation of the SCL, since SDA

transitions on the bus may be interpreted as a START or

STOP while SCL is high. The START and STOP

conditions on the bus must be generated in software. After

the serial data has been transmitted, the generation of the

ACK/NACK clock must be enabled by writing 0xFFh to

I2CDATA. This allows the master to read the state of

ACK/NACK.

Receive

The serial data is latched into the receive buffer on the

rising edge of SCL. After the serial data has been received,

ACK/NACK is generated by writing 0x7Fh (for ACK) or

0xFFh (for NACK) to I2CDATA.

SDA

SCL

1−7

STOP

Condition(4)

START

Condition(1)

ACK(3)

R/W(2)

DATA(2)

ADDRESS(2)

91−78

1−7

(1) Generate in software; write 0x7F to I2CDATA.

(2) I2CDATA register.

(3) Generate in software. Can enable bit count = 1 interrupt prior to ACK/NACK for interrupt use.

Generate ACK by writing 0x7F to I2CDATA; generate NACK by writing 0xFF to I2CDATA.

(4) Generate in software; write 0xFF to I2CDATA.

NOTES:

Figure 19. Timing Diagram for I2C Transmission and Reception

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