MSC1202Y2RHHT datasheet(35/92 Pages) TI1

35 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

www.ti.com

Figure 21 illustrates the Register Map. It is entirely

separate from the Program and Data Memory areas

discussed previously. A separate class of instructions is

used to access the registers. There are 256 potential

bytes of Scratchpad RAM and up to 128 SFRs. This is

possible since the upper 128 Scratchpad RAM locations

can only be accessed indirectly. Thus, a direct reference

to one of the upper 128 locations must be an SFR access.

Direct RAM is reached at locations 0 to 7Fh (0 to 127).

FFh

255

128

FFh

80h

7Fh

00h

Indirect

RAM

Direct

RAM

Scratchpad

RAM

SFR Registers

Direct

Special Function

Registers

255

128

127

Figure 21. Register Map

SFRs are accessed directly between 80h and FFh (128 to

255). The RAM locations between 128 and 255 can be

reached through an indirect reference to those locations.

Scratchpad RAM is available for general-purpose data

storage. Within the 128 bytes of RAM, there are several

special-purpose areas.

Bit Addressable Locations

In addition to direct register access, some individual bits

are also accessible. These are individually addressable

bits in both the RAM and SFR area. In the Scratchpad

RAM area, registers 20h to 2Fh are bit-addressable. This

provides 128 (16

× 8) individual bits available to software.

A bit access is distinguished from a full-register access by

the type of instruction. In the SFR area, any register

location ending in a 0h or 8h is bit-addressable. Figure 22

shows details of the on-chip RAM addressing including the

locations of individual RAM bits.

Working Registers

As part of the lower 128 bytes of RAM, there are four banks

of Working Registers, as shown in Figure 20. The Working

Registers are general-purpose RAM locations that can be

addressed in a special way. They are designated R0

through R7. Since there are four banks, the currently

selected bank will be used by any instruction using R0−R7.

This design allows software to change context by simply

switching banks. Bank access is controlled via the

Program Status Word register (PSW; 0D0h) in the SFR

area described below. The 16 bytes immediately above

the R0−R7 registers are bit-addressable, so any of the 128

bits in this area can be directly accessed using

bit-addressable instructions.

7Fh

2Fh

2Dh

2Eh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22h

21h

20h

1Fh

18h

17h

10h

0Fh

08h

07h

00h

Direct

RAM

Bank 3

Bank 2

Bank 1

Bank 0

MSB

LSB

Figure 22. Scratchpad Register Addressing

Thus, an instruction can designate the value stored in R0

(for example) to address the upper RAM. The 16 bytes

immediately

above

the

these

registers

are

bit-addressable, so any of the 128 bits in this area can be

directly accessed using bit-addressable instructions.

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