MSC1202Y2RHHT datasheet(31/92 Pages) TI1

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MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

www.ti.com

1) SS Asserted

2) First SCK Edge

3) CNTIF Set (dependent on CPHA bit)

4) SS Negated

SCK Cycle #

MSB

321

LSB

MSB

654

LSB

SlaveCPHA = 0Transfer inProgress

123

SlaveCPHA = 1Transfer inProgress

Sample Input

(CPHA = 0) Data Out

(CPHA = 1) Data Out

Sample Input

SS to Slave

SCK (CPOL = 0)

SCK (CPOL = 1)

Figure 18. SPI Timing Diagram

The SS pin can be used to control the output of data on

DOUT when the MSC120x is in slave mode. The SS

function is enabled or disabled by the ESS bit of the

SPICON SFR. When enabled, the SS input of a slave

device must be externally asserted before a master device

can exchange data with the slave device. SS must be low

before data transactions and must stay low for the duration

of the transaction. When SS is high, data will not be shifted

into the shift register, nor will the counter increment. When

SPI is enabled, SS also controls the drive of the line DOUT

(P1.2). When SS is low in slave mode, the DOUT pin will

be driven and when SS is high, DOUT will be high

impedance.

The SPI generates interrupt ECNT (AIE.2) to indicate that

the transfer/reception of the byte is complete. The interrupt

goes high whenever the counter value is equal to 8

(indicating that eight SCKs have occurred). The interrupt

is cleared on reading or writing to the SPIDATA register.

During the data transfer, the actual counter value can be

read from the SPICON SFR.

Power Down

The SPI is powered down by the PDSPI bit in the power

control register (PDCON). This bit needs to be cleared to

enable the SPI function. When the SPI is powered down,

pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose

I/O pins.

Application Flow

This section explains the typical application usage flow of

SPI in master and slave modes.

Master Mode Application Flow

Configure the port pins.

Configure the SPI.

Assert SS to enable slave communication (if

applicable).

Write data to SPIDATA.

Generate eight SCKs.

Read the received data from SPIDATA.

Slave Mode Application Flow

Configure the ports pins.

Enable SS (if applicable).

Configure the SPI.

Write data to SPIDATA.

Wait for the Count Interrupt (eight SCKs).

Read the data from SPIDATA.

CAUTION:

If SPIDATA is not read before the next SPI

transaction, the ECNT interrupt will be removed

and the previous data will be lost.

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