MSC1202Y2RHHT datasheet(52/92 Pages) TI1

52 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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Configuration Address (CADDR) (write-only)

Reset Value

SFR 93h

00h

CADDR

Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash Configuration

bits 7−0

Memory. It is recommended that faddr_data_read be used when accessing Configuration memory.This register is

also used as the address for the sfr_read and sfr_write routines, so it must be set prior to their use.

CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.

Configuration Data (CDATA) (read-only)

Reset Value

SFR 94h

00h

CDATA

Configuration Data. This register will contain the data in the 128 bytes of Flash Configuration Memory that

bits 7−0

is located at the last written address in the CADDR register. This is a read-only register.

Serial Port 0 Control (SCON0)

Reset Value

SFR 98h

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00h

SM0−2

Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in

bits 7−5

addition to the 8 or 9 data bits.

MODE

SM0

SM1

SM2

FUNCTION

LENGTH

PERIOD

Synchronous

8 bits

12 pCLK(1)

Synchronous

8 bits

4 pCLK(1)

Asynchronous

10 bits

Timer 1 Baud Rate Equation

Asynchronous−Valid Stop Required(2)

10 bits

Timer 1 Baud Rate Equation

Asynchronous

11 bits

64 pCLK(1) (SMOD = 0)

32 pCLK(1) (SMOD = 1)

Asynchronous with Multiprocessor Communication

11 bits

64 pCLK(1) (SMOD = 0)

32 pCLK(1) (SMOD = 1)

Asynchronous

11 bits

Timer 1 Baud Rate Equation

Asynchronous with Multiprocessor Communication(3)

11 bits

Timer 1 Baud Rate Equation

(1) p

CLK will be equal to tCLK, except that pCLK will stop for Idle mode.

(2) RI_0 will only be activated when a valid STOP is received.

(3) RI_0 will not be activated if bit 9 = 0.

REN_0

Receive Enable. This bit enables/disables the serial Port 0 received shift register.

bit 4

0: Serial Port 0 reception disabled.

1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).

TB8_0

9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.

bit 3

RB8_0

9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes

bit 2

2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.

TI_0

Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial

bit 1

port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit.

This bit must be manually cleared by software.

RI_0

Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial

bit 0

port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming

stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must

be manually cleared by software.

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