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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC5644AF0MLU2 датащи(PDF) 118 Page - Freescale Semiconductor, Inc |
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SPC5644AF0MLU2 датащи(HTML) 118 Page - Freescale Semiconductor, Inc |
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118 / 138 page  MPC5644A Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 118 3.17.9 eQADC SSI timing Figure 32. eQADC SSI timing Table 49. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)1 1 SS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. CLOAD = 25 pF on all outputs. Pad drive strength set to maximum. # Symbol C Rating Min Typ Max Unit 1fFCK CC D FCK Frequency 2, 3 2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number. 1/17 1 2fSYS_CLK 1tFCK CC D FCK Period (tFCK = 1/ fFCK) 2 17 tSYS_CLK 2tFCKHT CC D Clock (FCK) High Time tSYS_CLK 6.5 9* tSYS_CLK 6.5 ns 3tFCKLT CC D Clock (FCK) Low Time tSYS_CLK 6.5 8* tSYS_CLK 6.5 ns 4tSDS_LL CC D SDS Lead/Lag Time -7.5 7.5 ns 5tSDO_LL CC D SDO Lead/Lag Time -7.5 7.5 ns 6tDVFE CC D Data Valid from FCK Falling Edge (tFCKLT+tSDO_LL) 1ns 7tEQ_SU CC D eQADC Data Setup Time (Inputs) 22 ns 8tEQ_HO CC D eQADC Data Hold Time (Inputs) 1 ns 1st (MSB) 2nd 25th 26th 1st (MSB) 2nd 25th 26th 8 7 5 6 5 4 4 3 1 3 2 1 2 FCK SDS SDO External Device Data Sample at SDI eQADC Data Sample at FCK Falling Edge FCK Rising Edge |
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