AM79C970A datasheet(139/219 Pages) AMD

139 / 219 page

P R E L I M I N A R Y

AMD

139

Am79C970A

(CSR0, bit 11) will be set to ONE,

and an interrupt may be gener-

ated, depending upon the setting

of the MERRM bit (CSR3, bit 11)

and the IENA bit (CSR0, bit 6).

The value in this register is inter-

preted as the unsigned number

of XTAL1 clock periods divided

by two, i.e. the value in this regis-

ter is given in 0.1

µs increments.

For example, the value 0600h

(1536 decimal) will cause a

MERR to be indicated after

153.6

µs of bus latency. A value

of ZERO will allow an infinitely

long bus latency, i.e. bus timeout

error will never occur.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. This register is

set to 0600h by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

CSR112: Missed Frame Count

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

MFC

Missed Frame Count. Indicates

the number of missed frames.

MFC will roll over to a count of

ZERO from the value 65535. The

MFCO bit (CSR4, bit 8) will be set

each time that this occurs. The

PCnet-PCI II controller will not

count missed frames while the

device is in suspend mode

(SPND = 1, CSR5, bit 0).

Read accessible always. MFC is

read only, write operations are

ignored. MFC is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

CSR114: Receive Collision Count

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

RCC

Receive Collision Count. Indi-

cates

the

total

number

collisions

the

network

encountered by the receiver

since

the

last

reset

the counter.

RCC will roll over to a count of

ZERO from the value 65535. The

RCVCCO bit of CSR4 (bit 5) will

be set each time that this occurs.

The PCnet-PCI II controller will

continue counting collisions on

the network while the device is

in suspend mode (SPND = 1,

CSR5, bit 0)

Read accessible always. RCC is

read only, write operations are ig-

nored.

RCC

cleared

H_RESET or S_RESET or by

setting the STOP bit.

CSR122: Advanced Feature Control

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–2

RES

Reserved locations. Written as

ZEROs and read as undefined.

RCVALGN

Receive Frame Align. When set,

this bit forces the data field of

ISO 8802-3 (IEEE/ANSI 802.3)

frames to align to DWord ad-

dress boundaries. It is important

to note that this feature will only

function correctly if all receive

buffer boundaries are DWord

aligned and all receive buffers

have 0 MOD 4 lengths. In order to

accomplish the data alignment,

the PCnet-PCI II controller sim-

ply inserts two bytes of random

data at the beginning of the re-

ceive frame (i.e. before the ISO

8802-3 (IEEE/ANSI 802.3) desti-

nation address field). The MCNT

field reported to the receive de-

scriptor will not include the extra

two bytes.

Read/Write accessible always.

RCVALGN

cleared

H_RESET or S_RESET and is

not affected by STOP.

CSR124: Test Register 1

Bit

Name

Description

This register is used to place

the PCnet-PCI II controller into

various test modes. Only Runt

Packet Accept and GPSI port en-

able are user accessible test

modes. All other test modes are

for AMD internal use only.

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