AM79C970A datasheet(135/219 Pages) AMD

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AMD

135

Am79C970A

transmit descriptor. This counter

interprets the value in CSR78 as

pointing to the first descriptor. A

counter value of ZERO corre-

sponds to the last descriptor in

the ring.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR76: Receive Descriptor Ring Length

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 RCVRL

Receive Descriptor Ring Length.

Contains the two’s complement

of the receive descriptor ring

length. This register is initialized

during the PCnet-PCI II controller

initialization routine based on the

value in the RLEN field of the in-

itialization block. However, the

ring length can be programmed

to any value from 1 to 65535 by

writing directly to this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR78: Transmit Descriptor Ring Length

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 XMTRL

Transmit

Descriptor

Ring

Length.

Contains

the

two’s

complement of the transmit de-

scriptor ring length. This register

is initialized during the PCnet-

PCI II controller initialization rou-

tine based on the value in the

TLEN field of the initialization

block. However, the ring length

can be programmed to any value

from 1 to 65535 by writing directly

to this register.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR80: DMA Transfer Counter and FIFO

Watermark Control

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–14

RES

Reserved locations. Read as

ONEs and written as ZEROs. Ac-

cessible only when either the

STOP or the SPND bit is set.

13–12RCVFW[1:0]

Receive

FIFO

Watermark.

RCVFW specifies the number of

bytes which must be present in

the receive FIFO (once the frame

has been verified as a non-runt)

before

receive

DMA

re-

quested. If the network interface

is operating in half-duplex mode,

at least 64 bytes or a complete

frame must be received in order

for a receive DMA to start. This

effectively avoids having to react

to receive frames which are runts

or suffer a collision during the slot

time (512 bit times). If the Runt

Packet Accept feature is enabled

or if the network interface is oper-

ating in full-duplex mode, receive

DMA will be requested as soon

as either the Receive FIFO Wa-

termark is reached, or a com-

plete valid receive frame is

detected (regardless of length). If

the EADI interface is active and

the Runt Packet Accept feature is

enabled or the network interface

operating

full-duplex

mode, RCVFW must not be

programmed to 00b to allow

enough time to reject the frame.

Table 26. Receive Watermark Programming

RCVFW[1:0]

Bytes Received

128

Reserved

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. RCVFW is set

to a value of 01b (64 bytes) after

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

11–10XMTSP[1:0]

Transmit Start Point. As soon as

the number of bytes in the trans-

mit FIFO reaches the XMTSP

value, the PCnet-PCI II controller

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