AM79C970A datasheet(136/219 Pages) AMD

136 / 219 page

AMD

P R E L I M I N A R Y

136

Am79C970A

starts trying to transmit. When

the entire frame is in the FIFO,

transmission attempts will start

regardless

the

value

XMTSP. If the network interface

is operating in half-duplex mode,

regardless of XMTSP, the FIFO

will not internally overwrite its

data until at least 64 bytes (or the

entire frame if shorter than 64

bytes) have been transmitted

onto the network. This ensures

that for collisions within the slot

time window, transmit data need

not be reloaded into the transmit

FIFO, and retries will be handled

autonomously by the MAC. If the

Disable Retry feature is enabled,

or if the network is operating in

full-duplex mode, the PCnet-PCI

II controller can overwrite the be-

ginning of the frame as soon as

the data is transmitted, because

no collision handling is required

in these modes.

Table 27. Transmit Start Point Programming

XMTSP[1:0]

Bytes Written

128

248

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. XMTSP is set to

a value of 01b (64 bytes) after

H_RESET or S_RESET and

is unaffected by setting the

STOP bit.

9–8 XMTFW[1:0]

Transmit

FIFO

Watermark.

XMTFW controls the point at

which

transmit

DMA

re-

quested. Transmit DMA is re-

quested when the number of

bytes specified by XMTFW can

be written to the transmit FIFO.

Table 28. Transmit Watermark Programming

XMTFW[1:0]

Byte Spaces Available

128

Reserved

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. XMTFW is set to

value

00b

(16

bytes)

after H_RESET or S_RESET

and is unaffected by setting the

STOP bit.

7–0 DMATC[7:0]

DMA

Transfer

Counter.

DMAPLUS (CSR4, bit 14) is

cleared to ZERO, this counter

contains the maximum number

of FIFO read or write data phases

the PCnet-PCI II controller will

perform during a single bus mas-

tership period, if not preempted.

The DMA Transfer Counter is not

used to limit the number of data

phases during initialization block

or descriptor transfers. A value of

ZERO will be interpreted as one

data phase. If DMAPLUS is set to

ONE, the DMA Transfer Counter

is disabled, and the PCnet-PCI II

controller will try to transfer data

as long as the transmit FIFO is

not full or as long as the receive

FIFO is not empty.

When the PCnet-PCI II controller

is preempted and the last data

phase has finished, DMATC will

freeze. It will continue counting

down when the PCnet-PCI II

controller is granted bus owner-

ship again and continues with the

data transfers.

DMATC should not be enabled

when the PCnet-PCI II controller

is used in a PCI bus application.

The PCI Latency Timer should be

the only entity governing the time

the PCnet-PCI II controller has

control over the bus.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Note that the

read operation will yield the value

of the run-time copy of the DMA

Transfer Counter and not the

that

holds

the

pro-

grammed value. Most read op-

erations will yield a value of

ZERO, because the run-time

counter is only reloaded with

the programmed value at the be-

ginning of a new bus mastership

period.

The

DMA

Transfer

Counter is set to a value of

16 (10h) after H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

AM79C970A датащи(PDF) 136 Page - Advanced Micro Devices

AM79C970A датащи(HTML) 136 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL