AM79C970A datasheet(140/219 Pages) AMD

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Am79C970A

Table 29. GPSI Mode Pin Configuration

PCnet-PCI II

Controller

C-LANCE

Controller

Expansion

GPSI Function

GPSI I/O Type

GPSI Pin

Pin Number

ROM Pin

Collision

CLSN

ERD3

Receive Clock

RCLK

RXCLK

ERD1

Receive Data

RXDAT

ERD0

Receive Enable

RENA

RXEN

ERD2

Transmit Clock

TCLK

TXCLK

ERD4

Transmit Data

TXDAT

ERD7

Transmit Enable

TENA

TXEN

ERD6

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–5

RES

Reserved locations. Written as

ZEROs and read as undefined.

GPSIEN

General Purpose Serial Interface

Enable. This mode will recon-

figure some of the Expansion

ROM interface pins so that the

GPSI port is exposed. This

allows bypassing the MENDEC

and T-MAU logic. The PORTSEL

bits (CSR15, bits 8–7) must be

set to 10b in addition to program-

ming the GPSIEN bit in order to

select the GPSI port as the active

network port.

Read accessible always. Write

accessible when EN124 (CSR4,

bit 15) is set to ONE. GPSIEN

cleared

H_RESET

S_RESET and is not affected by

setting the STOP bit.

RPA

Runt Packet Accept. This bit

forces the PCnet-PCI II controller

to accept runt packets (packets

shorter than 64 bytes).

Read accessible always. Write

accessible when EN124 (CSR4,

bit 15) is set to ONE. RPA

cleared

H_RESET

S_RESET and is not affected by

setting the STOP bit.

2–0

RES

Reserved locations. Written as

ZEROs and read as undefined.

Bus Configuration Registers

The Bus Configuration Registers (BCRs) are used to

program the configuration of the bus interface and other

special features of the PCnet-PCI II controller that are

not related to the IEEE 8802-3 MAC functions. The

BCRs are accessed by first setting the appropriate

RAP value, and then by performing a slave access to

the BDP.

All BCR registers are 16 bits wide in Word I/O mode

(DWIO = 0, BCR18, bit 7) and 32 bits wide in DWord I/O

mode (DWIO = 1). The upper 16 bits of all BCR registers

are undefined when in DWord I/O mode. These bits

should be written as ZEROs and should be treated as

undefined when read. The default value given for any

BCR is the value in the register after H_RESET. Some

of these values may be changed shortly after H_RESET

when the contents of the external EEPROM is automati-

cally read in. With the exception of DWIO (BCR18, bit 7)

BCR register values are not affected by S_RESET.

None of the BCR register values are affected by the as-

sertion of the STOP bit.

Note that several registers have no default value. BCR0,

BCR1, BCR3, BCR8, BCR10–17 and BCR21 are re-

served and have undefined values. The content of

BCR2 is undefined until is has been first programmed

through the EEPROM read operation or a user register

write operation.

BCR0, BCR1, BCR16, BCR17 and BCR21 are registers

that are used by other devices in the PCnet family. Writ-

ing to these registers has no effect on the operation of

the PCnet-PCI II controller.

Writes to those registers marked as Reserved will have

no effect. Reads from these locations will produce

undefined values.

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