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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C970A датащи(PDF) 133 Page - Advanced Micro Devices |
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AM79C970A датащи(HTML) 133 Page - Advanced Micro Devices |
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133 / 219 page  P R E L I M I N A R Y AMD 133 Am79C970A Table 25. Software Styles SWSTYLE Style Initialization Descriptor Ring Altered Bit [7:0] Name CSRPCNET SSIZE32 Block Entries Entries Interpretations 00h C-LANCE 1 0 16-bit software 16-bit software All bits in CSR4 / structures, non-burst structures, non-burst are used, TMD1[29] PCnet-ISA or burst access access only is ADD_FCS 01h ILACC 0 1 32-bit software 32-bit software access CSR4[9:8],CSR4[5:4] structures, non-burst structures, non-burst and CSR4[1:0] have or burst access access only no function, TMD1[29] is NO_FCS. 02h PCnet- 1 1 32-bit software 32-bit software All bits in CSR4 are PCI II structures, non-burst structures, non-burst used, TMD1[29] is or burst access access only ADD_FCS 03h PCnet- 1 1 32-bit software 32-bit software All bits in CSR4 are PCI II structures, non-burst structures, non-burst used, TMD1[29] is controller or burst access or burst access ADD_FCS All Other Reserved Undefined Undefined Undefined Undefined Undefined CSR60: Previous Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PXDAL Contains the lower 16 bits of the previous transmit descriptor ad- dress pointer. The PCnet-PCI II controller can stack multiple transmit frames. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR61: Previous Transmit Descriptor Address Upper Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PXDAU Contains the upper 16 bits of the previous transmit descriptor ad- dress pointer. The PCnet-PCI II controller can stack multiple transmit frames. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR62: Previous Transmit Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. 11–0 PXBC Previous Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the previous transmit descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR63: Previous Transmit Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PXST Previous Transmit Status. This field is a copy of bits 31–16 of TMD1 of the previous transmit descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. |
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