AM79C970A datasheet(115/219 Pages) AMD

115 / 219 page

P R E L I M I N A R Y

AMD

115

Am79C970A

Read/Write accessible always.

STOP is set by writing a ONE, by

H_RESET or S_RESET. Writing

a ZERO has no effect. STOP is

cleared by setting either STRT

or INIT.

STRT

STRT assertion enables the

PCnet-PCI II controller to send

and receive frames and perform

buffer management operations.

Setting STRT clears the STOP

bit.

STRT

and

INIT

are

set together, the PCnet-PCI II

controller initialization will be

performed first.

Read/Write accessible always.

STRT is set by writing a ONE.

Writing a ZERO has no effect.

STRT is cleared by H_RESET,

S_RESET or by setting the

STOP bit.

INIT

assertion

enables

the

PCnet-PCI II controller to begin

the initialization procedure which

reads the initialization block from

memory. Setting INIT clears the

STOP bit. If STRT and INIT are

set together, the PCnet-PCI II

controller initialization will be per-

formed first. INIT is not cleared

when the initialization sequence

has completed.

Read/Write accessible always.

INIT is set by writing a ONE. Writ-

ing a ZERO has no effect. INIT is

cleared by H_RESET, S_RESET

or by setting the STOP bit.

CSR1: Initialization Block Address 0

Bit

Name

Description

This register is aliased with

CSR16.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 IADR[15:0]

Lower 16 bits of the address of

the initialization block. Bit loca-

tions 1 and 0 must both be ZERO

to align the initialization block to a

DWord boundary.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Unaffected by

H_RESET or S_RESET or by

setting the STOP bit.

CSR2: Initialization Block Address 1

Bit

Name

Description

This register is aliased with

CSR17.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–8IADR[31:24]

If SSIZE32 (BCR20, bit 8) is

cleared

ZERO,

then

the

IADR[31:24] bits will be used to

generate the upper 8 bits of all

bus mastering addresses, as

required for a 32-bit address bus.

Note that the 16-bit software

structures will yield only 24 bits of

address for PCnet-PCI II control-

ler bus master accesses. The

PCnet-PCI II controller is de-

signed for 32-bit systems which

require

bits

address.

Therefore, whenever SSIZE32 is

cleared

ZERO,

the

IADR[31:24] bits will be ap-

pended to the 24-bit initialization

address, to each 24-bit descrip-

tor base address and to each

beginning 24-bit buffer address

in order to form complete 32-bit

addresses. The upper 8 bits that

exist in the descriptor address

registers and the buffer address

registers which are stored on

board the PCnet-PCI II controller

will

overwritten

with

the

IADR[31:24] value, so that CSR

accesses to these registers will

show the 32 bit address that in-

cludes the appended field.

If SSIZE32 is set to ONE, then

the IADR[31:24] bits will be used

strictly as the upper 8 bits of

the initialization block address.

In this mode, software will pro-

vide 32-bit pointer values for all

of the shared software struc-

tures— i.e. descriptor bases and

buffer addresses.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Unaffected by

H_RESET, S_RESET or by set-

ting the STOP bit.

7–0 IADR[23:16]

Bits 23 through 16 of the address

of the initialization block.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Unaffected by

H_RESET, S_RESET or by set-

ting the STOP bit.

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