AM79C970A datasheet(106/219 Pages) AMD

106 / 219 page

AMD

P R E L I M I N A R Y

106

Am79C970A

in either of these lists can be assumed to be intended for

diagnostic purposes.

PCI Configuration Registers

The following is a list of those registers that would typi-

cally need to be programmed once during the initializa-

tion of the PCnet-PCI II controller within a system:

s PCI I/O Base Address or Memory Mapped I/O Base

Address register

s PCI Expansion ROM Base Address register

s PCI Interrupt Line register

s PCI Latency Timer register

s PCI Status register

s PCI Command register

Setup Registers

The following is a list of those registers that would typi-

cally need to be programmed once during the setup of

the PCnet-PCI II controller within a system. The control

bits in each of these registers typically do not need to be

modified once they have been written. However, there

are no restrictions as to how many times these registers

may actually be accessed. Note that if the default power

up values of any of these registers is acceptable to the

application, then such registers need never be ac-

cessed at all. Registers marked with “^” may be pro-

grammable through the EEPROM read operation, and

therefore do not necessarily need to be written to by the

system initialization procedure or by the driver software.

Registers marked with “*” will be initialized by the initiali-

zation block read operation.

CSR1

Initialization Block Address[15:0]

CSR2

Initialization Block Address[31:16]

CSR3

Interrupt Masks and Deferral Control

CSR4

Test and Features Control

CSR5

Extended Control and Interrupt

CSR8*

Logical Address Filter[15:0]

CSR9*

Logical Address Filter[31:16]

CSR10*

Logical Address Filter[47:32]

CSR11*

Logical Address Filter[63:48]

CSR12*

Physical Address[15:0]

CSR13*

Physical Address[31:16]

CSR14*

Physical Address[47:32]

CSR15*

Mode

CSR24*

Base Address of Receive Descriptor

Ring Lower

CSR25*

Base Address of Receive Descriptor

Ring Upper

CSR30*

Base Address of Transmit Descriptor

Ring Lower

CSR31*

Base Address of Transmit Descriptor

Ring Upper

CSR47

Polling Interval

CSR76*

Receive Descriptor Ring Length

CSR78*

Transmit Descriptor Ring Length

CSR82

Bus Activity Timer

CSR100

Memory Error Timeout

CSR122

Receiver Packet Alignment Control

BCR2^

Miscellaneous Configuration

BCR4^

Link Status LED

BCR5^

LED1 Status

BCR6^

LED2 Status

BCR7^

LED3 Status

BCR9^

Full-Duplex Control

BCR18^

Bus and Burst Control

BCR20

Software Style

Running Registers

The following is a list of those registers that would typi-

cally need to be periodically read and perhaps written

during the normal running operation of the PCnet-PCI II

controller within a system. Each of these registers con-

tains control bits or status bits or both.

RAP

CSR0

PCnet-PCI II Controller Status

CSR4

Test and Features Control

CSR5

Extended Control and Interrupt

CSR112

Missed Frame Count

CSR114

Receive Collision Count

PCI Status register

PCI Configuration Registers

PCI Vendor ID (Offset 00h)

The PCI Vendor ID register is a 16-bit register that iden-

tifies the manufacturer of the PCnet-PCI II controller.

Advanced Micro Devices, Inc.’s (AMD) Vendor ID is

1022h. Note that this vendor ID is not the same as the

Manufacturer ID in CSR88 and CSR89. The vendor ID is

assigned by the PCI Special Interest Group.

The PCI Vendor ID register is located at offset 00h in the

PCI Configuration Space. It is read only.

PCI Device ID Register (Offset 02h)

The PCI Device ID register is a 16-bit register that

uniquely identifies the PCnet-PCI II controller within

AMD’s product line. The PCnet-PCI II controller Device

ID is 2000h. Note that this Device ID is not the same as

the Part number in CSR88 and CSR89. The Device ID is

assigned by Advanced Micro Devices, Inc.

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