AM79C970A datasheet(107/219 Pages) AMD

107 / 219 page

P R E L I M I N A R Y

AMD

107

Am79C970A

The PCI Device ID register is located at offset 02h in the

PCI Configuration Space. It is read only.

PCI Command Register (Offset 04h)

The PCI Command register is a 16-bit register used to

control the gross functionality of the PCnet-PCI II con-

troller. It controls the PCnet-PCI II controller’s ability to

generate and respond to PCI bus cycles. To logically

disconnect the PCnet-PCI II controller device from all

PCI bus cycles except Configuration cycles, a value of

ZERO should be written to this register.

The PCI Command register is located at offset 04h in the

PCI Configuration Space. It is read and written by

the host.

Bit

Name

Description

15–10

RES

Reserved locations. Read as

ZEROs, write operations have

no effect.

FBTBEN

Fast Back-to-Back Enable. Read

as ZERO, write operations have

no effect. The PCnet-PCI II con-

troller will not generate Fast

Back-to-Back cycles.

SERREN

SERR enable. Controls the as-

sertion of the

SERR pin. SERR is

disabled

when

SERREN

cleared.

SERR will be asserted

on detection of an address parity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN

cleared

H_RESET and is not effected by

S_RESET or by setting the

STOP bit.

ADSTEP

Address/data stepping. Read as

ZERO, write operations have

no effect. The PCnet-PCI II

controller

does

not

use

address stepping.

PERREN

Parity Error Response enable.

Enables the parity error re-

sponse

functions.

When

PERREN is “0” and the PCnet-

PCI II controller detects a parity

error, it only sets the Detected

Parity Error bit in the PCI Status

the PCnet-PCI II controller as-

serts

PERR on the detection of a

data parity error. It also sets the

DATAPERR

bit

(PCI

Status

parity error occurred during a

master cycle. PERREN also en-

ables reporting address parity er-

rors through the

SERR pin and

the

SERR bit in the PCI

Status register.

PERREN

cleared

H_RESET and is not effected by

S_RESET or by setting the

STOP bit.

VGASNOOP

VGA palette snoop. Read as

ZERO, write operations have

no effect.

MWIEN

Memory Write and Invalidate Cy-

cle enable. Read as ZERO, write

operations have no effect. The

PCnet-PCI II controller only gen-

erates Memory Write cycles.

SCYCEN

Special Cycle enable. Read as

ZERO, write operations have

no effect. The PCnet-PCI II

controller ignores all Special

Cycle operations.

BMEN

Bus

Master

enable.

Setting

BMEN enables the PCnet-PCI II

controller to become a bus mas-

ter on the PCI bus. The host must

set BMEN before setting the INIT

or STRT bit in CSR0 of the

PCnet-PCI II controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

MEMEN

Memory Space access enable.

The PCnet-PCI II controller will

ignore all memory accesses

when MEMEN is cleared. The

host must set MEMEN before

the

first

memory

access

the device.

For memory mapped I/O, the

host must program the PCI Mem-

ory Mapped I/O Base Address

dress before setting MEMEN.

For accesses to the Expansion

ROM, the host must program the

PCI

Expansion

ROM

Base

Address register at offset 30h

with a valid memory address

before

setting

MEMEN.

The

PCnet-PCI II controller will only

respond to accesses to the Ex-

pansion

ROM

when

both

ROMEN (PCI Expansion ROM

Base Address register, bit 0)

and MEMEN are set to ONE.

Since MEMEN also enables the

memory

mapped

access

the PCnet-PCI II controller I/O

resources,

the

PCI

Memory

Mapped I/O Base Address regis-

ter must be programmed with an

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