AM79C970A datasheet(102/219 Pages) AMD

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Am79C970A

terminate all network activity in an orderly sequence be-

fore issuing an S_RESET.

STOP

A STOP reset is generated by the assertion of the STOP

bit in CSR0. Writing a ONE to the STOP bit of CSR0,

when the stop bit currently has a value of ZERO, will in-

itiate a STOP reset. If the STOP bit is already a ONE,

then writing a ONE to the STOP bit will not generate a

STOP reset.

STOP will reset all or some portions of CSR0, 3, and 4 to

default values. For the identity of individual CSRs and bit

locations that are affected by STOP, see the individual

CSR register descriptions. STOP will not affect any of

the BCR and PCI configuration space locations. STOP

will cause the microcode program to jump to its reset

state. Following the end of the STOP operation, the

PCnet-PCI II controller will not attempt to read the

EEPROM device. Setting the STOP bit does not affect

the T-MAU.

Note that STOP will not cause a deassertion of the

REQ

signal, if it happens to be active at the time of the

write to CSR0. The PCnet-PCI II controller will wait

until it gains bus ownership and it will first finish all

scheduled bus master accesses before the STOP reset

is executed.

STOP terminates all network activity abruptly. The host

can use the suspend mode (SPND, CSR5, bit 0) to ter-

minate all network activity in an orderly sequence before

setting the STOP bit.

Software Access

PCI Configuration Registers

The PCnet-PCI II controller implements a 256-byte con-

figuration space as defined by the PCI specification

revision 2.0. The 64-byte header includes all registers

required to identify the PCnet-PCI II controller and its

function. Additional registers are used to setup the con-

figuration of the PCnet-PCI II controller in a system.

None of the device specific registers located at offsets

40h through FCh are implemented. The layout of the

PCnet-PCI II controller PCI configuration space is

shown in the table below.

The PCI configuration registers are accessible only by

configuration cycles. All multi-byte numeric fields follow

little endian byte ordering. All write accesses to Re-

served locations have no effect; reads from these loca-

tions will return a data value of ZERO.

Table 18. PCI Configuration Space Layout

Device ID

Vendor ID

00h

Status

Command

04h

Base-Class

Sub-Class

Programming IF

Revision ID

08h

Reserved

Header Type

Latency Timer

Reserved

0Ch

I/O Base Address

10h

Memory Mapped I/O Base Address

14h

Reserved

18h

Reserved

1Ch

Reserved

20h

Reserved

24h

Reserved

28h

Reserved

2Ch

Expansion ROM Base Address

30h

Reserved

34h

Reserved

38h

MAX_LAT

MIN_GNT

Interrupt Pin

Interrupt Line

3Ch

Reserved

40h

Reserved

FCh

24 23

16 15

Offset

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