AM79C970A datasheet(108/219 Pages) AMD

108 / 219 page

AMD

P R E L I M I N A R Y

108

Am79C970A

address so that the device does

not claim cycles not intended

for it.

MEMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

IOEN

I/O Space access enable. The

PCnet-PCI II controller will ignore

all I/O accesses when IOEN is

cleared. The host must set IOEN

before the first I/O access to the

device.

The

PCI

I/O

Base

Address

must

programmed with a valid I/O ad-

dress before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

PCI Status Register (Offset 06h)

The PCI Status register is a 16-bit register that contains

status information for the PCI bus related events. It is lo-

cated at offset 06h in the PCI Configuration Space.

Bit

Name

Description

PERR

Parity Error. PERR is set when

the PCnet-PCI II controller de-

tects a parity error.

The PCnet-PCI II controller sam-

ples the AD[31:0], C/

BE[3:0] and

the PAR lines for a parity error at

the following times:

slave

mode,

during

the

address

phase

any

PCI

bus command.

In slave mode, for all I/O, mem-

ory

and

configuration

write

commands

that

select

the

PCnet-PCI II controller when

data is transferred (

TRDY and

IRDY are asserted).

In master mode, during the

data

phase

all

memory

read commands.

In master mode, during the data

phase of the memory write com-

mand, the PCnet-PCI II controller

sets the PERR bit if the target re-

ports a data parity error by as-

serting the

PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the PCnet-PCI II

controller and cleared by writing

a ONE. Writing a ZERO has no

effect.

PERR

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

SERR

Signaled SERR. SERR is set

when the PCnet-PCI II controller

detects an address parity error,

and both SERREN and PERREN

(PCI Command register, bits 8

and 6) are set.

SERR is set by the PCnet-PCI II

controller and cleared by writing

a ONE. Writing a ZERO has no

effect.

SERR

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

RMABORT

Received

Master

Abort.

RMABORT is set when the

PCnet-PCI II controller termi-

nates a master cycle with a mas-

ter abort sequence.

RMABORT

set

the

PCnet-PCI

controller

and

cleared by writing a ONE. Writing

ZERO

has

effect.

RMABORT

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

RTABORT

Received

Target

Abort.

RTABORT is set when a target

terminates a PCnet-PCI II con-

troller master cycle with a target

abort sequence.

RTABORT

set

the

PCnet-PCI

controller

and

cleared by writing a ONE. Writing

ZERO

has

effect.

RTABORT

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

STABORT

Send Target Abort. Read as

ZERO, write operations have

no effect. The PCnet-PCI II con-

troller will never terminate a

slave

access

with

target

abort sequence.

STABORT is read only.

10–9 DEVSEL

Device Select timing. DEVSEL is

set to 01b (medium), which

means that the PCnet-PCI II

controller will assert

DEVSEL

two clock periods after

FRAME

is asserted.

DEVSEL is read only.

DATAPERR

Data

Parity

Error

detected.

DATAPERR is set when the

PCnet-PCI II controller is the cur-

rent bus master and it detects a

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