AM79C970A datasheet(103/219 Pages) AMD

103 / 219 page

P R E L I M I N A R Y

AMD

103

Am79C970A

I/O Resources

The PCnet-PCI II controller requires 32 bytes of address

space for access to all the various internal registers as

well as to some setup information stored in an external

serial EEPROM. A software reset port is available, too.

The PCnet-PCI II controller supports mapping the ad-

dress space to both I/O and memory space. The value in

the PCI I/O Base Address register determines the start

address of the I/O address space. The register is typi-

cally programmed by the PCI configuration utility after

system power-up. The PCI configuration utility must

also set the IOEN bit in the PCI Command register to en-

able I/O accesses to the PCnet-PCI II controller. For

memory mapped I/O access, the PCI Memory Mapped

I/O Base Address register controls the start address of

the memory space. The MEMEN bit in the PCI Com-

mand register must also be set to enable the mode. Both

base address registers can be active at the same time.

The PCnet-PCI II controller supports two modes for ac-

cessing the I/O resources. For backwards compatibility

with AMD’s 16-bit Ethernet controllers, Word I/O is the

default mode after power up. The device can be config-

ured to DWord I/O mode by software.

I/O Registers

The PCnet-PCI II controller registers are divided into

two groups. The Control and Status Registers (CSR)

are used to configure the Ethernet MAC engine and to

obtain status information. The Bus Control Registers

(BCR) are use to configure the bus interface unit and the

LEDs. Both sets of registers are accessed using

indirect addressing.

The CSR and BCR share a common Register Address

Port (RAP). There are, however, separate data ports.

The Register Data Port (RDP) is used to access a CSR.

The BCR Data Port (BDP) is used to access a BCR.

In order to access a particular CSR location, the RAP

should first be written with the appropriate CSR ad-

dress. The RDP will then points to the selected CSR. A

read of the RDP will yield the selected CSR data. A write

to the RDP will write to the selected CSR. In order to ac-

cess a particular BCR location, the RAP should first be

written with the appropriate BCR address. The BDP will

then points to the selected BCR. A read of the BDP will

yield the selected BCR data. A write to the BDP will write

to the selected BCR.

Once the RAP has been written with a value, the RAP

value remains unchanged until another RAP write oc-

curs, or until an H_RESET or S_RESET occurs. RAP is

cleared to all ZEROs when an H_RESET or S_RESET

occurs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The PCnet-PCI II controller allows for connection of a

serial EEPROM. The first 16 bytes of the EEPROM will

be automatically loaded into the Address PROM

(APROM) space after H_RESET. The Address PROM

space is a convenient place to store the value of the

48-bit IEEE station address. It can be overwritten by the

host computer. Its content has no effect on the operation

of the controller. The software must copy the station ad-

dress from the Address PROM space to the initialization

block or to CSR12-14 in order for the receiver to accept

unicast frames directed to this station.

The 6 bytes of IEEE station address occupy the first 6

locations of the Address PROM space. The next six

bytes are reserved. Bytes 12 and 13 should match the

value of the checksum of bytes 1 through 11 and 14 and

15. Bytes 14 and 15 should each be ASCII W (57h). The

above requirements must be met in order to be compat-

ible with AMD driver software.

The APROMWE bit (BCR2, bit 8) must be set to ONE to

enable write access to the Address PROM space.

Reset Register

A read of the Reset register creates an internal software

reset (S_RESET) pulse in the PCnet-PCI II controller.

The internal S_RESET pulse that is generated by this

access is different from both the assertion of the

hardware

RST pin (H_RESET) and from the assertion of

the software STOP bit. Specifically, S_RESET is the

equivalent of the assertion of the

RST pin (H_RESET)

except that S_RESET has no effect on the BCR or PCI

Configuration space locations or on the T-MAU.

The NE2100 LANCE based family of Ethernet cards

requires that a write access to the Reset register

follows each read access to the Reset register. The

PCnet-PCI II controller does not have a similar require-

ment. The write access is not required but it does not

have any effects.

Note that the PCnet-PCI II controller cannot service any

slave accesses for a very short time after a read access

of the Reset register, because the internal S_RESET

operation takes about 1

µs to finish. The PCnet-PCI II

controller will terminate all slave accesses with the as-

sertion of

DEVSEL and STOP while TRDY is not as-

serted, signaling to the initiator to disconnect and retry

the access at a later time.

Word I/O Mode

After H_RESET, the PCnet-PCI II controller is pro-

grammed to operate in Word I/O mode. DWIO (BCR18,

bit 7) will be cleared to ZERO. The table below shows

how the 32 bytes of address space are used in Word

I/O mode.

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