PIC10LF322T-EMCSQTP datasheet(51/210 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

Preliminary

DS41585A-page 51

PIC10(L)F320/322

7.0

POWER-DOWN MODE (SLEEP)

The Power-down mode is entered by executing a

SLEEP

instruction.

Upon entering Sleep mode, the following conditions

exist:

WDT will be cleared but keeps running, if

enabled for operation during Sleep.

PD bit of the STATUS register is cleared.

TO bit of the STATUS register is set.

CPU clock is disabled.

31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

ADC is unaffected, if the dedicated FRC clock is

selected.

I/O ports maintain the status they had before

SLEEP

was executed (driving high, low or high-

impedance).

Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following condi-

tions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• CWG and NCO modules using HFINTOSC

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching cur-

rents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include the FVR module. See Section 12.0

“Fixed Voltage Reference (FVR)”

for more informa-

tion on these modules.

7.1

Wake-up from Sleep

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin, if enabled

BOR Reset, if enabled

POR Reset

Watchdog Timer, if enabled

Any external interrupt

Interrupts by peripherals capable of running dur-

ing Sleep (see individual peripheral for more

information)

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section 5.9

“Determining the Cause of a Reset”

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP

instruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

The Complementary Waveform Generator (CWG) and

the Numerically Controlled Oscillator (NCO) modules

can utilize the HFINTOSC oscillator as their respective

clock source. Under certain conditions, when the HFIN-

TOSC is selected for use with the CWG or NCO mod-

ules, the HFINTOSC will remain active during Sleep.

This will have a direct effect on the Sleep mode current.

Please refer to 21.0 “Complementary Waveform

Generator (CWG) Module”

and 20.0 “Numerically

Controlled Oscillator (NCO) Module”

for more infor-

mation.

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