PIC10LF322T-EMCSQTP datasheet(46/210 Pages) MICROCHIP

46 / 210 page

PIC10(L)F320/322

DS41585A-page 46

Preliminary

 2011 Microchip Technology Inc.

6.6

Interrupt Control Registers

6.6.1

INTCON REGISTER

The INTCON register is a readable and writable

for TMR0 register overflow, interrupt-on-change and

external INT pin interrupts.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

R-0/0

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

GIE:

Global Interrupt Enable bit

= Enables all active interrupts

= Disables all interrupts

bit 6

PEIE:

Peripheral Interrupt Enable bit

= Enables all active peripheral interrupts

= Disables all peripheral interrupts

bit 5

TMR0IE:

Timer0 Overflow Interrupt Enable bit

= Enables the Timer0 interrupt

= Disables the Timer0 interrupt

bit 4

INTE:

INT External Interrupt Enable bit

= Enables the INT external interrupt

= Disables the INT external interrupt

bit 3

IOCIE:

Interrupt-on-Change Interrupt Enable bit

= Enables the interrupt-on-change interrupt

= Disables the interrupt-on-change interrupt

bit 2

TMR0IF:

Timer0 Overflow Interrupt Flag bit

= TMR0 register has overflowed

= TMR0 register did not overflow

bit 1

INTF:

INT External Interrupt Flag bit

= The INT external interrupt occurred

= The INT external interrupt did not occur

bit 0

IOCIF:

Interrupt-on-Change Interrupt Flag bit(1)

= When at least one of the interrupt-on-change pins changed state

= None of the interrupt-on-change pins have changed state

Note 1:

The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register

have been cleared by software.

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