PIC10LF322T-EMCSQTP datasheet(48/210 Pages) MICROCHIP

48 / 210 page

PIC10(L)F320/322

DS41585A-page 48

Preliminary

 2011 Microchip Technology Inc.

6.6.3

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 6-3.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

R/W-0/0

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—ADIF

—

NCO1IF

CLC1IF

—TMR2IF

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

Unimplemented

: Read as ‘0’

bit 6

ADIF:

A/D Converter Interrupt Flag bit

= The A/D conversion completed

= The A/D conversion is not complete

bit 5

Unimplemented

: Read as ‘0’

bit 4

NCO1IF:

Numerically Controlled Oscillator Interrupt Flag bit

= NCO1 overflow occurred (must be cleared in software)

= No NCO1 overflow

bit 3

CLC1IF:

Configurable Logic Block Rising Edge Interrupt Flag bit

= CLC interrupt occurred (must be cleared in software)

= No CLC Interrupt

bit 2

Unimplemented

: Read as ‘0’

bit 1

TMR2IF:

TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match

Note:

The match must occur the number of times specified by the TMR2 postscaler (Register 17-1).

bit 0

Unimplemented

: Read as ‘0’

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