PIC12F635ESS datasheet(124/234 Pages) MICROCHIP

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PIC12F635/PIC16F636/639

DS41232D-page 122

FIGURE 11-19:

DETAILED SPI INTERFACE TIMING (AFE)

11.32.2.1

Clamp On Command

This command results in activating (turning on) the

modulation transistors of all enabled channels; channels

enabled in Configuration Register 0 (Register 11-1).

11.32.2.2

Clamp Off Command

This command results in de-activating (turning off) the

modulation transistors of all channels.

11.32.2.3

Sleep Command

This command places the AFE in Sleep mode –

minimizing current draw by disabling all but the

essential circuitry. Any other command wakes the AFE

(example: Clamp Off command).

11.32.2.4

Soft Reset Command

The AFE issues a Soft Reset when it receives an

external Soft Reset command. The external Soft Reset

command is typically used to end a SPI communication

sequence or to initialize the AFE for the next signal

detection sequence, etc. See Section 11.20 “Soft

Reset” for more details on Soft Reset.

If a Soft Reset command is sent during a “Clamp-on”

condition, the AFE still keeps the “Clamp-on” condition

after the Soft Reset execution. The Soft Reset is

executed in Active mode only, not in Standby mode.

The SPI Soft Reset command is ignored if the AFE is

not in Active mode.

11.32.2.5

AGC Preserve On Command

This command results in preserving the AGC level

during each AGC settling time and apply the value to

the data slicing circuit for the following data stream. The

preserved AGC value is reset by a Soft Reset, and a

new AGC value is acquired and preserved when it

starts a new AGC settling time. This feature is disabled

by an AGC Preserve Off command (see Section 11.19

“AGC Preserve”).

11.32.2.6

AGC Preserve Off Command

This command disables the AGC preserve feature and

returns the AFE to the normal AGC tracking mode, fast

tracking during AGC settling time and slow tracking

after that (see Section 11.19 “AGC Preserve”).

11.32.3

CONFIGURATION REGISTERS

The AFE includes 8 Configuration registers, including a

column parity register and AFE Status Register. All

registers are readable and writable via SPI, except

STATUS register, which is readable only. Bit 0 of each

number.

SCLK

SDIO

Command

Data Byte

Address

Row

Parity Bit

MSb

LSb

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