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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC12F635ESS датащи(PDF) 128 Page - Microchip Technology |
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PIC12F635ESS датащи(HTML) 128 Page - Microchip Technology |
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128 / 234 page  PIC12F635/PIC16F636/639 DS41232D-page 126 © 2007 Microchip Technology Inc. REGISTER 11-6: CONFIGURATION REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AUTOCHSEL AGCSIG MODMIN1 MODMIN0 LCZSEN3 LCZSEN2 LCZSEN1 LCZSEN0 R5PAR bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 AUTOCHSEL: Auto Channel Select bit 1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of TSTAB; or otherwise, blocks the channel(s). 0 = Disabled – AFE follows channel enable/disable bits defined in Register 0 bit 7 AGCSIG: Demodulator Output Enable bit, after the AGC loop is active 1 = Enabled – No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set when the AGC begins regulating. 0 = Disabled – the AFE passes signal of any level it is capable of detecting bit 6-5 MODMIN<1:0>: Minimum Modulation Depth bit 00 =50% 01 =75% 10 =25% 11 =12% bit 4-1 LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit 0000 = -0dB (Default) : 1111 = -30dB bit 0 R5PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits Note 1: Assured monotonic increment (or decrement) by design. REGISTER 11-7: COLUMN PARITY REGISTER 6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 COLPAR7 COLPAR6 COLPAR5 COLPAR4 COLPAR3 COLPAR2 COLPAR1 COLPAR0 R6PAR bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Configuration register row parity bits contain an odd number of set bits. bit 7 COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 6 COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 5 COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 4 COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 3 COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 2 COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 1 COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Configuration Registers 0 through 5 contain an odd number of set bits. bit 0 R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits |
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