PIC12F635ESS datasheet(19/234 Pages) MICROCHIP

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DS41232D-page 17

PIC12F635/PIC16F636/639

2.0

MEMORY ORGANIZATION

2.1

Program Memory Organization

The PIC12F635/PIC16F636/639 devices have a 13-bit

program counter capable of addressing an 8K x 14

program memory space. Only the first 1K x 14

(0000h-03FFh, for the PIC12F635) and 2K x 14

(0000h-07FFh, for the PIC16F636/639) is physically

implemented. Accessing a location above these

boundaries will cause a wraparound within the first

2K x 14 space. The Reset vector is at 0000h and the

interrupt vector is at 0004h (see Figure 2-1).

2.2

Data Memory Organization

The data memory (see Figure 2-2) is partitioned into

two banks, which contain the General Purpose

Registers (GPR) and the Special Function Registers

(SFR). The Special Function Registers are located in

the first 32 locations of each bank. Register locations

20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs,

implemented as static RAM for the PIC16F636/639.

For the PIC12F635, register locations 40h through 7Fh

are GPRs implemented as static RAM. Register

locations F0h-FFh in Bank 1 point to addresses

70h-7Fh in Bank 0. All other RAM is unimplemented

and returns ‘0’ when read. RP0 of the STATUS register

is the bank select bit.

RP1

RP0

→ Bank 0 is selected

→ Bank 1 is selected

→ Bank 2 is selected

→ Bank 3 is selected

FIGURE 2-1:

PROGRAM MEMORY MAP AND

STACK OF THE PIC12F635

FIGURE 2-2:

PROGRAM MEMORY MAP AND

STACK OF THE PIC16F636/639

PC<12:0>

0000h

0004h

0005h

03FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0400h

Access 0-3FFh

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

Access 0-7FFh

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