PIC12F635ESS datasheet(30/234 Pages) MICROCHIP

30 / 234 page

PIC12F635/PIC16F636/639

DS41232D-page 28

2.2.2.3

INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, PORTA change and

external RA2/INT pin interrupts.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

RAIE(1,3)

T0IF(2)

INTF

RAIF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

= Enables all unmasked interrupts

= Disables all interrupts

bit 6

PEIE: Peripheral Interrupt Enable bit

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

bit 5

T0IE: Timer0 Overflow Interrupt Enable bit

= Enables the Timer0 interrupt

= Disables the Timer0 interrupt

bit 4

INTE: RA2/INT External Interrupt Enable bit

= Enables the RA2/INT external interrupt

= Disables the RA2/INT external interrupt

bit 3

RAIE: PORTA Change Interrupt Enable bit(1,3)

= Enables the PORTA change interrupt

= Disables the PORTA change interrupt

bit 2

T0IF: Timer0 Overflow Interrupt Flag bit(2)

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 1

INTF: RA2/INT External Interrupt Flag bit

= The RA2/INT external interrupt occurred (must be cleared in software)

= The RA2/INT external interrupt did not occur

bit 0

RAIF: PORTA Change Interrupt Flag bit

= When at least one of the PORTA general purpose I/O pins changed state (must be cleared in

software)

= None of the PORTA general purpose I/O pins have changed state

Note 1:

IOCA register must also be enabled.

T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

Includes ULPWU interrupt.

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