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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC12F635ESS датащи(PDF) 123 Page - Microchip Technology |
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PIC12F635ESS датащи(HTML) 123 Page - Microchip Technology |
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123 / 234 page  © 2007 Microchip Technology Inc. DS41232D-page 121 PIC12F635/PIC16F636/639 11.32.2 COMMAND DECODER/CONTROLLER The circuit executes 8 SPI commands from the MCU. The command structure is: Command (3 bits) + Configuration Address (4 bits) + Data Byte and Row Parity Bit received by the AFE Most Significant bit first. Table 11-5 shows the available SPI commands. The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19). SDI data is loaded into the AFE on the rising edge of SCLK and SDO data is clocked out on the falling edge of SCLK. There must be multiples of 16 clocks (SCLK) while CS is low or commands will abort. TABLE 11-5: SPI COMMANDS (AFE) Command Address Data Row Parity Description Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless. 000 XXXX XXXX XXXX X Clamp on – enable modulation circuit 001 XXXX XXXX XXXX X Clamp off – disable modulation circuit 010 XXXX XXXX XXXX X Enter Sleep mode (any other command wakes the AFE) 011 XXXX XXXX XXXX X AGC Preserve On – to temporarily preserve the current AGC level 100 XXXX XXXX XXXX X AGC Preserve Off – AGC again tracks strongest input signal 101 XXXX XXXX XXXX X Soft Reset – resets various circuit blocks Read Command – Data will be read from the specified register address. 110 0000 Config Byte 0 P General – options that may change during normal operation 0001 Config Byte 1 P LCX antenna tuning and LFDATA output format 0010 Config Byte 2 P LCY antenna tuning 0011 Config Byte 3 P LCZ antenna tuning 0100 Config Byte 4 P LCX and LCY sensitivity reduction 0101 Config Byte 5 P LCZ sensitivity reduction and modulation depth 0110 Column Parity P Column parity byte for Config Byte 0 -> Config Byte 5 0111 AFE Status X AFE status – parity error, which input is active, etc. Write Command – Data will be written to the specified register address. 111 0000 Config Byte 0 P General – options that may change during normal operation 0001 Config Byte 1 P LCX antenna tuning and LFDATA output format 0010 Config Byte 2 P LCY antenna tuning 0011 Config Byte 3 P LCZ antenna tuning 0100 Config Byte 4 P LCX and LCY sensitivity reduction 0101 Config Byte 5 P LCZ sensitivity reduction and modulation depth 0110 Column Parity P Column parity byte for Config Byte 0 -> Config Byte 5 0111 Not Used X Register is readable, but not writable Note: ‘P’ denotes the row parity bit (odd parity) for the respective data byte. |
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