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PIC12F635ESS датащи(PDF) 125 Page - Microchip Technology |
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PIC12F635ESS датащи(HTML) 125 Page - Microchip Technology |
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125 / 234 page ![]() © 2007 Microchip Technology Inc. DS41232D-page 123 PIC12F635/PIC16F636/639 TABLE 11-6: ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY Register Name Address Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Configuration Register 0 0000 OEH OEL ALRTIND LCZEN LCYEN LCXEN R0PAR Configuration Register 1 0001 DATOUT Channel X Tuning Capacitor R1PAR Configuration Register 2 0010 RSSIFET CLKDIV Channel Y Tuning Capacitor R2PAR Configuration Register 3 0011 Unimplemented Channel Z Tuning Capacitor R3PAR Configuration Register 4 0100 Channel X Sensitivity Control Channel Y Sensitivity Control R4PAR Configuration Register 5 0101 AUTOCHSEL AGCSIG MODMIN MODMIN Channel Z Sensitivity Control R5PAR Column Parity Register 6 0110 Column Parity Bits R6PAR AFE Status Register 7 0111 Active Channel Indicators AGCACT Wake-up Channel Indicators ALARM PEI REGISTER 11-1: CONFIGURATION REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OEH1 OEH0 OEL1 OEL0 ALRTIND LCZEN LCYEN LCXEN R0PAR bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8-7 OEH<1:0>: Output Enable Filter High Time (TOEH) bit 00 = Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA) 01 =1 ms 10 =2 ms 11 =4 ms bit 6-5 OEL<1:0>: Output Enable Filter Low Time (TOEL) bit 00 =1 ms 01 =1 ms 10 =2 ms 11 =4 ms bit 4 ALRTIND: ALERT bit, output triggered by: 1 = Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 “Alarm Timer”) 0 = Parity error bit 3 LCZEN: LCZ Enable bit 1 = Disabled 0 = Enabled bit 2 LCYEN: LCY Enable bit 1 = Disabled 0 = Enabled bit 1 LCXEN: LCX Enable bit 1 = Disabled 0 = Enabled bit 0 R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits |
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