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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LSM6DB0 датащи(PDF) 36 Page - STMicroelectronics |
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LSM6DB0 датащи(HTML) 36 Page - STMicroelectronics |
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36 / 66 page  Microprocessor functionality LSM6DB0 36/66 DocID025603 Rev 1 8.13 JTAG and SW debug support The ARM JTAG debug port is embedded which enables debug using a standard JTAG connection. The ARM serial wire debug port is also embedded which enables serial wire debug to be connected to the CPU. The JTAG TMS and TCK pins are shared with the SW_TDIO and SW_TCK respectively. There are two mechanisms to select the debug mode. JTAG debug mode is selected by setting the IO9 pin to zero. During reset, the SW debug mode is selected by default. Figure 16. Debug mode selection timing 1. RESETN needs an external pull-up if not driven 1. Default option depending on software configuration Table 14. Debug mode selection POR IO9 Debug mode 0 0 JTAG: SOC(1) + CPU TAP(2) selected 1. SOC = chip and processor 2. TAP = test access port 0 1 SW: CPU TAP(2) selected 1X(3) 3. X = don’t care JTAG or SW available |
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