LSM6DB0 datasheet(23/66 Pages) STMICROELECTRONICS

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LSM6DB0

Device operating modes

6.3

Microprocessor operating modes

Several microprocessor operating modes are defined for the LSM6DB0:



Reset mode



Two low-power modes: low-power wait-for-interrupt (WFI) mode and high-power wait-

for-interrupt (WFI) mode



Active mode

In reset mode the LSM6DB0 is in ultra-low-power consumption: no voltage regulators, nor

clocks are powered. The LSM6DB0 enters reset mode by asserting the external reset

signal.

While in low-power WFI mode, the LSM6DB0 CPU is stopped and the high-frequency

80 MHz RC oscillator is powered down. All peripherals, apart from one timer, are disabled.

The power consumption is about 800 μA with a 1 kHz clock.

In high-power WFI mode, the CPU is stopped and the high-frequency 80 MHz RC oscillator

is powered up. This mode allows a faster response time for an interrupt to wake up the

CPU. All peripherals are enabled and can wake up the CPU with an interrupt. The power

consumption in this mode is around 2 mA with an 80 MHz clock.

In active mode the LSM6DB0 is fully operational: all interfaces, including SPI, I2C, JTAG

and UART, are active as well as all internal power supplies together with the high-speed

frequency oscillator. The MCU core is also running.

Table 11. Accelerometer turn-on time

ODR [Hz]

BW = 400 Hz(1)

1. The table contains the number of samples to be discarded after switching between power-down mode

and normal mode.

BW = 200 Hz(1)

BW = 100 Hz(1)

BW = 50 Hz(1)

14.9

59.5

119

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476

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