AD-DPGIOZ datasheet(27/61 Pages) AD

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Data Sheet

AD9961/AD9963

Rev. A | Page 27 of 60

Address

Bit(s)

Parameter

Function

Rx Scale

0x38

7:5

Unused

4:0

DEC_SCALE[4:0]

Value of 3.2 multiplier applied to both I and Q channels just after the

decimation filter. The value of the gain applied is equal to DEC_SCALE/4.

00000: multiply by 0.0.

00001: multiply by 0.25.

11111: multiply by 7.75.

Clock Doubler

Config

0x39

RXDDLLRST

1: resets the Rx signal path clock doubler.

TXDDLLRST

1: resets the Tx signal path clock doubler.

5:4

Unused

RXDBL_SEL

0: selects fixed pulse width clock doubler.

1: selects fixed duty cycle clock doubler.

See Table 22 for configuration recommendations.

TXDBL_SEL

0: selects fixed pulse width clock doubler.

1: selects fixed duty cycle clock doubler.

See Table 22 for configuration recommendations.

TX Clock Doubler

Config

0x3A

7:4

TX_UNLOCK[1:0]

Sets the number of clock cycles for the unlock indicator. Set to 01.

TX_LOCK[1:0]

Sets the number of clock cycles for the lock indicator. Set to 01.

TX_DLYOFS[1:0]

Sets delay line offset of clock doubler. Set to 01.

TX_HYST[1:0]

Sets delay line hysteresis of clock doubler. Set to 01.

RX Clock Doubler

Config

0x3B

7:4

RX_UNLOCK[1:0]

Sets the number of clock cycles for the unlock indicator. Set to 01.

RX_LOCK[1:0]

Sets the number of clock cycles for the lock indicator. Set to 01.

RX_DLYOFS[1:0]

Sets delay line offset of clock doubler. Set to 01.

RX_HYST[1:0]

Sets delay line hysteresis of clock doubler. Set to 01.

Clock Doubler

Config

0x3C

7:0

DBL_TAPDLY[7:0]

Sets the initial tap delay of the Rx and Tx clock doublers. Set to 0x00.

Data Spectral

Inversion

0x3D

7:4

Unused

RX_INVQ

1: multiply Rxdata from QADC by −1.

RX_INVI

1: multiply Rxdata from IADC by −1.

TX_INVQ

1: multiply Txdata for QDAC by −1.

TX_INVI

1: multiply Txdata for IDAC by −1.

Clock Doubler

Pulse Width

0x3E

7:6

Unused

5:3

TX_DBLPW[2:0]

Sets the pulse width of the Tx clock doubler. See Table 22 for details.

2:0

RX_DBLPW[2:0]

Sets the pulse width of the Rx clock doubler. See Table 22 for details.

Rx Data Interface

0x3F

Unused

RX_CLK

0: when SINGLERX is active, use Q side clock.

1: when SINGLERX is active, use I side clock.

RX_BUS

0: when SINGLERX is active, use the Q ADC.

1: when SINGLERX is active, use the I ADC.

SINGLERX

0: use both Rx paths.

1: use only one Rx path.

TXCLK_MD

This bit controls the operation of the TXCLK pin when the chip is

configured in half-duplex 1-clock mode. This bit is otherwise ignored.

0: the TXCLK pin is set to a high impedance output.

1: the DLL clock output is driven onto the TXCLK pin.

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