AD-DPGIOZ datasheet(40/61 Pages) AD

40 / 61 page

AD9961/AD9963

Data Sheet

Rev. A | Page 40 of 60

WRITE

POINTER

I DAC

READ

POINTER

24 BITS

TXCLK

DACCLK

I DATA

PATH

DATA

FORMAT

INPUT

LATCH

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

FIFO_OFFSET

Reg 0x33[2:0]

Q DAC

Q DATA

PATH

FIFO

FIFO RESET

AND MONITOR

FIFO_PTR

Reg 0x34[7:0]

TXD[11:0]

TXIQ

RDCLK

WRCLK

TXSMPCLK

TX_BNRY

Reg 0x31[0]

TX_IFIRST

Reg 0x31[1]

TXIQ_HILO

Reg 0x31[2]

TXCLK_MD

Reg 0x31[1]

TXCKI_INV

Reg 0x31[3]

TXCKO_INV

Reg 0x31[6]

TXCLK_MD

Reg 0x31[0]

÷ I

÷ 2

DOUBLER

TX_SDR

Reg 0x31[7]

I = 1

TXDBL_SEL

TX_DBLPW[2:0]

Reg 0x39[0]

Reg 0x3E[5:3]

* I DENOTES INTERPOLATION RATIO

Figure 52. Transmit Path Data Flow and Clock Generation In Full Duplex Mode

The signal on the TXCLK pin can be configured as either an

input or an output. This is configured by the TXCLK_MD

variable (Register 0x31, Bits[5:4]). Whether configured as an

input or an output, the TXCLK signal has the option of being

inverted by configuring the TXCKI_INV or TXCKO_INV

variables.

The transmit path clock doubler is only used when all of the

interpolation filters are bypassed (I = 1) and the transmit path is

configured in bus rate mode (TX_SDR = 1). For more

information about configuring the clock doubler, see Table 22.

TRANSMIT DAC OPERATION

Figure 53 shows a simplified block diagram of one of the transmit

path DACs. Each DAC consists of a current source array, switch

core, digital control logic, and full-scale output current control.

The DAC contains a current source array capable of providing a

nominal full-scale current (IOUTFS) of 2 mA. The output currents

from the TXIP and TXIN pins are complementary, meaning that

the sum of the two currents always equals the full-scale current of

the DAC. The digital input code to the DAC determines the

effective differential current delivered to the load.

The DACs are powered through the TXVDD pin and can operate

over a 1.8 V to 3.3 V supply range. To facilitate interfacing the

output of the AD9961/AD9963 directly to a range of common-

mode levels, an internal bias voltage is made available through the

TXCML pin.

The DAC full-scale output current is regulated by the reference

control amplifier and is determined by the product of a reference

current, a programmable reference resistor, RREF, an internal

programmable resistor, RSET, and a pair of programmable gain

scaling parameters.

TXVDD

IGAIN1[5:0]

0x68[5:0]

IGAIN2

0x69[5:0]

100µA

REFIO

REFIO_ADJ[5:0]

0x6E[5:0]

IRSET[5:0]

0x6A[5:0]

TXDATA

IDAC

RREF

RSET

TX1P

TX1N

TXCML

DACCLK

Figure 53. Simplified Block Diagram of I DAC Core

Transmit DAC Transfer Function

The output currents from the TXIP and TXIN pins are

complementary, meaning that the sum of the two currents

always equals the full-scale current of the DAC. The digital

input code to the DAC determines the effective differential

current delivered to the load. TXIP provides maximum output

current when all bits are high. The output currents vs. DACCODE

for the DAC outputs are expressed as:

OUTFS

TXIP

DACCODE













(1)

TXIP

OUTFS

TXIN





(2)

where DACCODE = 0 to 2N − 1.

There are a number of adjustments that can be made to scale IOUTFS

to provide programmability in the output signal level.

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