AD-DPGIOZ datasheet(52/61 Pages) AD

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AD9961/AD9963

Data Sheet

Rev. A | Page 52 of 60

AUXILIARY CONVERTERS

The AD9961/AD9963 have two fast settling servo DACs, along

with an analog input and two analog I/O pins. All of the

auxiliary converters run off a dedicated supply pin. The input

and output compliance ranges depend on the voltage supplied.

AUXILIARY ADC

The auxiliary ADC is a 12-bit SAR converter that is accessed

and controlled through the serial port registers (Register 0x77

through Register 0x7B). The ADC voltage reference and clock

signals are generated on chip. The auxiliary ADC is preceded by

a seven-input multiplexer. The ADC inputs can be connected to

either the AUXIN1, AUXIO2, AUXIO3 input pins, or one of

four internal signals as shown in Figure 85.

AUX

DAC10A

AUXIN1

AUXIO2

AUXIO3

VCMLQ

VRxCML

VPTAT

VCMLI

CLK

2.5V

AUXREF

AUXADCCLK

110

100

101

011

000

001

010

REG 0x77[2:0]

SEL

REG 0x7A[2:0]

VINT

111

AUX

DAC10B

AUX

DAC

Figure 85. Block Diagram of Auxiliary ADC Circuitry

CONVERSION CLOCK

The auxiliary ADC conversion clock is generated through a

programmable binary division of the CLK input signal. The

frequency of the ADC conversion clock is programmable and

can be calculated from the following equation:

CLK

AUXCLK =

where R is programmed through Register 0x7A, Bits[2:0].

For best performance and lowest power consumption, the

conversion clock speed should be set to the lowest speed that

meets the system conversion time requirements. The maximum

allowable auxiliary ADC clock speed is 10 MHz.

Voltage Reference

The auxiliary ADC has an internal, temperature stable, 2.5 V

reference. This results in an input voltage range of 0 V to 3.2 V.

When using the internal voltage reference, the AUXADCREF

pin should be decoupled to AGND through a 0.22 µF capacitor.

The AUXADCREF pin can be used as a reference output to

external devices, but the current load on the pin should be

limited to sourcing less than 5 mA and sinking less than 100 µA.

For systems with tight accuracy requirements, a higher accuracy

external reference can be used to source a voltage into the

AUXADCREF pin. The input voltage range for external voltage

references is from 1.0 V to 2.5 V. The input impedance of the

AUXADCREF pin is 100 kΩ. The full-scale input voltage of the

ADC is a function of the voltage reference as:

AUXREF

AUXFS

Analog Inputs

The ADC can be configured to sample one of eight analog

inputs. The input is selected through the channels select bits

(Register 0x77, Bits[2:0]). These eight signals are described in

Table 28.

Table 28. Auxiliary ADC Channel Selections

Channel

Select

Signal

Description

000

AUXIN1

Pin 72.

001

AUXIO2

Pin 71. The auxiliary DAC10A should be

disabled when using this pin as an input.

010

AUXIO3

Pin 70. The auxiliary DAC10B should be

disabled when using this pin as an input.

011

VPTAT

Voltage proportional to absolute

temperature scaled to 0.2 °K per LSB.

Therefore, the temperature in degrees C

is:

273

)

(Co

−

CODE

ADC

100

VCMLI

Common mode level of the I and Q Rx

ADC buffers. Should measure

approximately 0.9 V. The buffer must be

enabled (see Configuration Register

0x7E).

101

VCMLQ

110

RXCML

The RXCML output voltage on Pin 10. This

should measure approximately 1.4 V.

111

GND

Should measure 0 V.

When selected, Input Pin 70, Pin 71, and Pin 72 are connected

to the sampling cap of the auxiliary ADC. Therefore, the

circuits driving these inputs need to recover to the desired

accuracy from having a discharged 10 pF capacitor connected

to it at the initiation of the conversion, within the sampling

window. A programmable delay (Register 0x7B, Bits[1:0]) can

be added to the conversion cycle time to allow additional

settling time of the input. If the ADC input is driven from a low

source impedance, like the output of an op amp, a 20-cycle

conversion time should yield good results. Higher impedance

sources may require the 34-cycle conversion time to fully settle.

Where the conversion cycle time is not an issue, it is

recommended that the full 34-cycle conversion time be used.

Conversions where the input multiplexer is switched between

inputs require a longer conversion cycle time than consecutive

conversions from the same multiplexer input.

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