AD-DPGIOZ datasheet(42/61 Pages) AD

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AD9961/AD9963

Data Sheet

Rev. A | Page 42 of 60

–8

–6

–4

–2

GAIN1

Figure 56. Typical DAC Full-Scale Current vs. GAIN1 Code

1.94

1.96

1.98

2.00

2.02

2.04

2.06

GAIN2

Figure 57. Typical DAC Full-Scale Current vs. GAIN2 Code

TRANSMIT DAC OUTPUTS

The optimum noise and distortion performances of the AD9961/

AD9963 are realized when they are configured for differential

operation. The common-mode error sources of the DAC outputs

are significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed waveform

increases and/or its amplitude increases. This is due to the first-

order cancellation of various dynamic common-mode distortion

mechanisms, digital feedthrough, and noise.

TXIP

TXIN

TXQP

TXQN

TXCML

–

VIP

VIN

VQP

VQN

VOUTQ

VOUTI

Figure 58. Basic Transmit DAC Output Circuit

Figure 58 shows the most basic DAC output circuitry. A pair of

resistors, RO, are used to convert each of the complementary

output currents to a differential voltage output, VOUTX. Because

the current outputs of the DAC are very high impedance, the

differential driving point impedance of the DAC outputs, ROUT,

is equal to 2 × RO.

Figure 59 illustrates the output voltage waveforms.

VPEAK

VOUT

VCM

–VPEAK

Figure 59. Voltage Output Waveforms

The common-mode signal voltage, VCM, is calculated as:

The peak output voltage, VPEAK, is calculated as:

PEAK

With this circuit configuration, the single-ended peak voltage is

the same as the peak differential output voltage.

Setting the TXCML Pin Voltage

The TXCML pin serves to change the DAC bias voltages in the

part, allowing it to operate with higher output signal common-

mode voltages. When the output signal common mode is below

0.8 V, the TXCML pin should be tied directly to AGND. When

the output signal common mode is greater then 0.8 V, then the

TXCML pin should be set to 0.5 V. The TXCML pin should be a

low ac impedance source (capacitive decoupling is

recommended).

When the TXVDD supply is 1.8 V, the output signal common-

mode voltage should be kept close to 0 V and the TXCML pin

should be connected directly to ground. When the TXVDD

supply is 3.3 V, the output signal common mode can be operated as

high as 1.25 V.

The circuit shown in Figure 60 shows a typical output circuit

configuration that provides a non zero bias voltage at the

TXCML pin. Resistance values of 499 Ω for RL and 249 Ω for

RCML produces a 2 V p-p differential output voltage swing with a

1.0 V output common-mode voltage and a voltage of 0.5 V

supplied to the TXCML pin. The 2 mA full-scale current flows

through the 249 Ω RCML creating the 0.5 V TXCML voltage. The

decoupling capacitor, assures a low ac driving impedance for

the TXCML pin.

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