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AD9961/AD9963

Data Sheet

Rev. A | Page 48 of 60

DIGITAL INTERFACES

The AD9961/AD9963 have two parallel interface ports, the

Tx port and the TRx port. The operation of the ports depends

on whether the device is configured for full-duplex or half-

duplex mode.

In full-duplex mode, the TRx and Tx port operate independently.

The TRx port outputs samples from the receive path and the Tx

port accepts incoming samples for the transmit port.

In half-duplex mode, the TRx port outputs samples from the

receive path and accepts incoming samples for the transmit

path. The Tx port is disabled. The operation of the digital

interface is detailed in the sections that follow.

TRX PORT OPERATION (FULL-DUPLEX MODE)

In full-duplex mode, the TRX port sources the data from the

AD9961/AD9963 I and Q receive channels. The interface

consists of an output data bus (TRXD[11:0]) that carries the

interleaved I and Q data. The data is accompanied by a

qualifying output clock (TRXCLK) and an output signal

(TRXIQ) that identifies the data as from either the I or Q

channel. The maximum guaranteed data rate is 200 MSPS.

The basic timing diagram for the Rx path is shown in Figure 72.

By default, the time-aligned TRXD[11:0] and TRXIQ output

signals are driven on the rising edge of the TRXCLK signal.

The tOD parameters are specified in Table 23.

TRXIQ

TRXD[11:0]

TRXCLK

tOD1

Figure 72. Receive Path Timing Diagram (Bus Rate Clock Mode)

An additional configuration bit, RXCLKPH, is available to

invert the TRXCLK. In this case, the TRX data and the TRXIQ

signals are driven out on the falling edge of TRXCLK and tOD is

measured with respect to the falling edge of TRXCLK.

The analog signals are sampled simultaneously, creating a

quadrature pair of data. This creates two possible data pairing

orders on the output bus, I data followed by Q data, or Q data

followed by I data. There are also two possible ways to align the

bus data with the TRXIQ signal, I data aligned with TRXIQ

being high or I data aligned with TRXIQ being low. The IQ

pairing and data to TRXIQ alignment relationships create four

possible timing modes. The AD9961/AD9963 enable any of

these four modes to be sourced from the device. The data

pairing order is controlled by the RX_IFIRST bit. The phase

relationship between the Rx data and the RXIQ signal is

controlled by the RXIQ_HILO bit. The two programming

options produce the four timing diagrams shown in Figure 73.

TRXIQ

TRXD[11 :0]

RX_IFIRST = 1

RXIQ_HILO = 1

RX_IFIRST = 1

RXIQ_HILO = 0

RX_IFIRST = 0

RXIQ_HILO = 1

RX_IFIRST = 0

RXIQ_HILO = 0

Figure 73. Receive Path Data Pairing Options

The output clock on TRXCLK can also be configured as a

double data rate (DDR) clock. In this mode the output clock is

divided by 2 and samples are placed on the TRXD[11:0] bus on

both the rising and falling edges of the TRXCLK. Figure 74

shows the timing.

TRXIQ

TRXD[11:0]

tOD2

TRXCLK

Figure 74. Receive Path Timing Diagram (DDR Clock Mode)

Table 23. Maximum Output Delay Between TRXCLK/

TRXD[11:0] and TRXIQ Signals from −40°C to +85°C

Parameter

Min

Max

Min

Max

Units

Drive

Strength

0x00

0xAA

tOD1

0.55

0.93

0.36

0.57

tOD2

0.42

0.67

0.20

0.35

SINGLE ADC MODE

The receive port can be operated with only one of the ADCs

operational. In this mode the TRXCLK signal can operate in

either bus rate clock mode or double data rate clock mode. The

TRXIQ pin indicates which ADC is active. Figure 75 to Figure 78

show the timing options available.

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