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Data Sheet

AD9961/AD9963

Rev. A | Page 55 of 60

POWER SUPPLIES

The AD9961/AD9963 power distributions are shown in Figure 93.

The functional blocks labeled Rx ANLG, Rx ADCs, SPI and

digital core, clocking, and DLL operate from 1.8 V supplies. The

functional blocks labeled Tx DACs, AUX DACs and digital I/O

operate over a supply voltage range from 1.8 V to 3.3 V. The

auxiliary ADC operates from a 3.3 V supply.

AUX ADCs

AUX DACs

Rx ANLG

DLL

CLOCKING

SPI AND

DIGITAL

CORE

Rx ADCs

AD9961/AD9963

Tx DACs

DIGITAL I/O

LDO

AUX33V

RX18V

RX33V

RX18VF

TXVDD(2)

DLL18V

CLK18V

DVDD18V

DRVDD(3)

CLK33V

Figure 93. AD9961/AD9963 Power Distribution Block Diagram

The 1.8 V only blocks can be supplied directly with 1.8 V by

using the RX18V, RX18VF, DLL18V, CLK18V, and DVDD18V

supply pins. In this mode, the on-chip voltage regulators must

be disabled. To provide optimal ESD protection for the device,

the inputs of the LDO regulators should not be left floating.

When unused, the LDO regulator inputs should be tied to one

of the LDO outputs (for example, if RX33V is unused, tie

RX33V to either RX18V or RX18VF).

When the LDO regulators are used, the RX18V, RX18VF,

DLL18V, CLK18V, and DVDD18V pins should be decoupled to

ground with a 0.1 μF or larger capacitor. The LDO inputs can

operate over a range from 2.5 V to 3.3 V.

The LDO_EN pin (Pin 14) is a three-state input pin that

controls the operation of the LDOs. When LDO_EN is high, all

of the LDOs are enabled. When LDO_EN is low, all of the

LDOs are disabled. When LDO_EN is floating or approximately

DRVDD/2, only the DVDD18V LDO is enabled. All of the

LDOs except the DVDD18V LDO can be independently

disabled through serial port control as well by writing to

The three DRVDD pins are internally connected together,

therefore, these pins must be connected to the same voltage.

The voltage applied to these pins affects the timing of the device

as noted in the Digital Interfaces section.

The TXVDD and AUX33V supplies can operate over a range

from 1.8 V to 3.3 V. It should be noted that the auxiliary ADC

requires AUX33V to be 3.3 V for operation. The performance

of the Tx DACs vary with the TXVDD supply as indicated in

the Table 1 and Figure 4 to Figure 11.

POWER SUPPLY CONFIGURATION EXAMPLES

There are numerous ways of configuring the power supplies

powering the AD9961/AD9963. Two power supply

configuration examples are shown in Figure 94 and Figure 95.

Figure 94 shows a 3.3 V only power supply configuration. In

this case, all of the internal circuits that require 1.8 V supplies

are powered from the on-chip regulators. The LDO_EN pin is

set high, and all of the internal LDOs are enabled. The transmit

DAC, auxiliary converters, and I/O pads run from a 3.3 V supply.

REG 0x61 = 0x00

3.3V

AD9961/AD9963

Figure 94. 3.3 V Only Supply Configuration

Figure 95 shows a power supply configuration where all 1.8 V

voltage rails are powered by external supplies. The LDO_EN

pin is grounded, and all of the internal LDOs are disabled. The

transmit DAC, auxiliary converters and I/O pads run from a

3.3 V supply.

3.3V

1.8V

AD9961/AD9963

Figure 95. 3.3 V and 1.8 V Supply Configuration

POWER DISSIPATION

The AD9961/AD9963 power dissipation is highly dependent on

operating conditions. Table 30 and Figure 96 to Figure 103 show

the typical current consumption by power supply domain under

different operating conditions.

The current draw from the 1.8 V supplies are independent of

whether they are supplied by the on-chip regulators or by an

external 1.8 V supply. The quiescent current of the LDO regulators

are about 100 μA.

The current drawn from the AUX33V supply by the auxiliary ADC

is typically 350 μA. The 10-bit auxiliary DACs each typically draw

275 μA from the AUX33V supply. The 12-bit auxiliary DACs

typically draw 550 μA each from the AUX33V supply.

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