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AM3703CUS датащи(PDF) 220 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 220 Page - Texas Instruments |
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220 / 280 page ![]() AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). (2) See Section 4.3.4, Processor Clocks. Table 6-66. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics —Falling Edge and Transmit Mode(1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 14.79 0.7 29.58 ns valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 14.79 0.6 29.58 ns mcbspx_dx valid Slave 0.6 13.89 0.6 28.68 ns (1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode on UART pins) and Set #3 (multiplexing mode on McBSP1 pins). (2) See Section 4.3.4, Processor Clocks. Table 6-67. McBSP4 (Set #1) Timing Requirements —Falling Edge and Transmit Mode(1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-69 and Table 6-70. (2) See Section 4.3.4, Processor Clocks. Table 6-68. McBSP4 (Set #1) Switching Characteristics —Falling Edge and Transmit Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.56 0.7 33.12 ns valid B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to Master 0.6 16.56 0.6 33.12 ns mcbspx_dx valid Slave 0.6 17.15 0.6 32.22 ns (1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-69 and Table 6-70. (2) See Section 4.3.4, Processor Clocks. Table 6-69. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements —Falling Edge and Transmit Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx 5.81 12.21 ns active edge B6 th(CLKXAE-FSXV) Hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are specified in Table 6-66 and Table 6-67. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins). (2) See Section 4.3.4, Processor Clocks. 220 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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