WM8978CGEFLSLASHV datasheet(31/118 Pages) WOLFSON

31 / 118 page

Production Data

WM8978

PD, Rev 4.5, October 2011

Figure 16 ADC Digital Filter Path

The ADCs are enabled by the ADCENL/R register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 2

ADCENL

Enable ADC left channel:

0 = ADC disabled

1 = ADC enabled

ADCENR

Enable ADC right channel:

0 = ADC disabled

1 = ADC enabled

Table 12 ADC Enable Control

The polarity of the output signal can also be changed under software control using the

ADCLPOL/ADCRPOL register bit.

The oversampling rate of the ADC can be adjusted using the

ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power

operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14

ADC Control

ADCLPOL

ADC left channel polarity adjust:

0=normal

1=inverted

ADCRPOL

ADC right channel polarity adjust:

0=normal

1=inverted

ADCOSR

ADC oversample rate select:

0=64x (lower power)

1=128x (best performance)

Table 13 ADC Control

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two

modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off

frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off

frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown

in Table 15.

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