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WM8978CGEFL/V датащи(PDF) 38 Page - Wolfson Microelectronics plc |
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WM8978CGEFL/V датащи(HTML) 38 Page - Wolfson Microelectronics plc |
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38 / 118 page ![]() WM8978 Production Data w PD, Rev 4.5, October 2011 38 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION … (time doubles with every step) 1010 or higher 23.2ms 186ms 1.34s Table 17 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL MODE In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this. Figure 17 ALC Normal Mode Operation |
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