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WM8978CGEFL/V датащи(PDF) 81 Page - Wolfson Microelectronics plc |
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WM8978CGEFL/V датащи(HTML) 81 Page - Wolfson Microelectronics plc |
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81 / 118 page ![]() Production Data WM8978 w PD, Rev 4.5, October 2011 81 The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all JD_EN0 or JD_EN1 settings. If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs to be controlled as normal via the normal output enables found in Table 49. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 GPIO control 5:4 JD_SEL 00 Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved 6 JD_EN 0 Jack Detection Enable 0 = disabled 1 = enabled 8:7 JD_VMID 00 [7] VMID_EN_0 [8] VMID_EN_1 R13 3:0 JD_EN0 0000 Output enables when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 7:4 JD_EN1 0000 Output enables when selected jack detection input is logic 1 0000-0011 = Reserved [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 Table 62 Jack Detect Register Control Bits |
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