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WM8978CGEFL/V датащи(PDF) 74 Page - Wolfson Microelectronics plc

номер детали WM8978CGEFL/V
подробное описание детали  Stereo CODEC with Speaker Driver
PDF  118 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8978CGEFL/V датащи(HTML) 74 Page - Wolfson Microelectronics plc

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WM8978
Production Data
w
PD, Rev 4.5, October 2011
74
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6
Clock
Generation
Control
0
MS
0
Sets the chip to be master over LRC and
BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs
generated by the WM8978 (MASTER)
4:2
BCLKDIV
000
Configures the BCLK output frequency,
for use when the chip is master over
BCLK.
000=divide by 1 (BCLK=SYSCLK)
001=divide by 2 (BCLK=SYSCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
8
CLKSEL
1
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
Table 54 Clock Control
The CLKSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from
MCLK (CLKSEL=0). When the internal clock is switched from one source to another using the
CLKSEL bit, the clock originally selected must generate at least one falling edge after CLKSEL has
changed for the switching of clocks to be successful.
EXAMPLE:
If the PLL is the current source of the internal clock (CLKSEL=1) and it is required to switch to the
MCLK, change CLKSEL to select MCLK (CLKSEL=0) and then disable PLL (PLLEN=0).



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