WM8978CGEFLSLASHV datasheet(48/118 Pages) WOLFSON

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WM8978

Production Data

PD, Rev 4.5, October 2011

Figure 24 DAC Digital Filter Path

The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC

analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker

(LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them

to output different signals to the headphone and speaker outputs.

DIGITAL PLAYBACK (DAC) PATH

Digital data is passed to the WM8978 via the flexible audio interface and is then passed through a

variety of advanced digital filters (as shown in Figure 24) to the hi-fi DACs. The DACs are enabled by

the DACENL/R register bits.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

Management 3

DACENL

Left channel DAC enable

0 = DAC disabled

1 = DAC enabled

DACENR

Right channel DAC enable

0 = DAC disabled

1 = DAC enabled

Table 26 DAC Enable Control

The WM8978 also has a Soft Mute function, which, when enabled, gradually attenuates the volume

of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This

function is enabled by default. To play back an audio signal, this function must first be disabled by

setting the SOFTMUTE bit to zero.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R10

DAC Control

DACPOLL

Left DAC output polarity:

0 = non-inverted

1 = inverted (180 degrees phase shift)

DACPOLR

Right DAC output polarity:

0 = non-inverted

1 = inverted (180 degrees phase shift)

AMUTE

Automute enable

0 = Amute disabled

1 = Amute enabled

DACOSR

DAC oversampling rate:

0=64x (lowest power)

1=128x (best performance)

SOFTMUTE

Softmute enable:

0=Enabled

1=Disabled

Table 27 DAC Control Register

The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital

interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a

high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and

sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low

distortion.

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