WM8978CGEFLSLASHV datasheet(87/118 Pages) WOLFSON

87 / 118 page

Production Data

WM8978

PD, Rev 4.5, October 2011

SYMBOL

MIN

TYPICAL

MAX

UNIT

tline_midrail_on

500

tline_midrail_off

thp_midrail_on

500

thp__midrail_off

tdacint

2/fs

/fs

DAC Group Delay

29/fs

/fs

Table 65 Typical POR Operation (typical simulated values)

Notes:

The lineout charge time, tline_midrail_on, is mainly determined by the VMID pin charge time. This time

is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and

AVDD power supply rise time. The values above were measured using a 4.7μF capacitor.

It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data

value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue

outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute

function has been applied to the signal beforehand.

The lineout discharge time, tline_midrail_off, is dependent upon the value of the lineout coupling

capacitor and the leakage resistance path to ground. The values above were measured using a

10μF output capacitor.

The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling

capacitor and VMID pin input resistance and AVDD power supply rise time. The values above

were measured using a 4.7μF VMID decoupling capacitor.

The headphone discharge time, thp_midrail_off, is dependent upon the value of the headphone

coupling capacitor and the leakage resistance path to ground. The values above were measured

using a 100μF capacitor.

The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for

normal DAC operation.

WM8978CGEFL/V датащи(PDF) 87 Page - Wolfson Microelectronics plc