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SPEAR1310 датащи(PDF) 47 Page - STMicroelectronics

номер детали SPEAR1310
подробное описание детали  Dual-core Cortex A9 embedded MPU for communications
PDF  57 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1310 датащи(HTML) 47 Page - STMicroelectronics

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SPEAr1310
One-time programmable antifuse (OTP)
Doc ID 17528 Rev 4
47/57
31
One-time programmable antifuse (OTP)
The OTP block is an array of one-time programmable antifuse memory cells.
All OTP banks feature an embedded charge pump which provides internally the high voltage
necessary for antifuse programming sessions. Therefore, it is not necessary to use an
additional high voltage pad at the chip interface. OTP is software programmable, so no
dedicated programming interface is needed at chip level.
31.1
Main features
OTP embeds three 255-bit banks, with these features:
BANK 1: 255-bit data bank with write-protect mechanism
BANK 2: 255-bit data bank with write-protect mechanism
BANK M: 255-bit bank, logically partitioned as follows:
32 bits (16 + redundancy) used for BANK1/BANK2 write protection
4 bits ( 2 + redundancy) reserved for selecting usage of 2 following sections (ID
and key)
72 bits free or reserved for USB/PCI ID data (64 + ECC)
137 bits free or reserved for key storage (128 + ECC)
2 bits ( 1 + redundancy) reserved for disabling ARM debug feature
8 bits reserved



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