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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR1310 датащи(PDF) 14 Page - STMicroelectronics |
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SPEAR1310 датащи(HTML) 14 Page - STMicroelectronics |
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14 / 57 page  Reset and clock generator (RCG) SPEAr1310 14/57 Doc ID 17528 Rev 4 5 Reset and clock generator (RCG) The reset and clock generator (RCG) provides the system clocks and resets. It is highly configurable through the miscellaneous registers. 5.1 Main features ● Three main clock sources: – osci1: 24 MHz clock coming from internal oscillator connected to external quartz. – osci2: 32 kHz clock coming from internal oscillator used for RTC block (optional) – osci3: 25/100 MHz clock coming from MIPHY macro (optional). ● Three programmable dithered PLLs (to reduce EMI): – PLL1: primarily used to generate the 1 GHz clock for the AMBA subsystem – PLL2, PLL3: primarily used to generate clocks for RAS logic and generic IPs ● Seven configurable clock generators: – SSCG1-4: dedicated to RAS logic – SSCG5: for CLCD clock – SSCG6: for EXPI clock – SSCG7: for AMBA system clocks ● Three operating modes for AMBA clocks: – DOZE: the clock source is osci2 (osci1 after power on) – SLOW: the clock source is the osci1 or a divided version – NORMAL: the clock source is PLL1 (by default), PLL2, PLL3 or SSCG7 ● Configurable clock gating and software reset for most peripherals ● Global software reset and watchdog reset |
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