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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR1310 датащи(PDF) 7 Page - STMicroelectronics |
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SPEAR1310 датащи(HTML) 7 Page - STMicroelectronics |
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7 / 57 page  SPEAr1310 Description Doc ID 17528 Rev 4 7/57 port can be programmed and optimized through an internal, weighted round-robin (WRR) arbitration scheme. Figure 2 is the internal connectivity block diagram. Figure 2. SPEAr1310 block diagram of the internal connectivity 2x Giga/Fast Ethernet 3x Fast Ethernet MCIF Memory card interface FSMC Flash/SRAM controller SMI Serial memory interface 1x USB OTG 2x UHC USB Host controller 2x HDLC (TDM/E1) EXPI Expansion interface C3 Crypto accelerator Reset and clock control 3x PCIe MPMC DDR2/3 controller 2x CAN 6x UART SSP 2x I2C ADC KBD keyboard 2x I2S RTC GPIO 2x DMAC A9 Subsystem Module G I C SCU cache2cache transfers Snoop filtering Timers FPU A9 CPU Instr Cache FPU PTM I/F A9 CPU Instr Cache Data Cache 32 KB BootROM Network-on-chip JPEG Codec 32 KB RAM Data Cache PTM F I/ L2 cache 2x HDLC (RS485) 3x SATA MISC Power management OTP memory Temp. sensor (THSENS) LCD display controller PCI 32-bit @ 66 MHz A C P |
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