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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR1310 датащи(PDF) 33 Page - STMicroelectronics |
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SPEAR1310 датащи(HTML) 33 Page - STMicroelectronics |
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33 / 57 page  SPEAr1310 TDM/E1 HDLC controller Doc ID 17528 Rev 4 33/57 20 TDM/E1 HDLC controller 20.1 Main features The main features of the TDM/E1 HDLC design are: ● AMBA 2.0 compliant ● AMBA slave interface, used to program TDM/E1 ● AMBA master interface, used to transfer data between DDR and IP ● DMA engine included to alleviate CPU from transferring data ● Data buffer queue making bulk data transfer more efficient ● Interrupt Queue supplying more interrupt information ● Miscellaneous Interrupt generation – Frame transmitted/received – End of data buffer queue – Buffer empty/ buffer filled – Tx/Rx DMA FIFO underflow/overflow – Interrupt queue overflow – Interrupt FIFO overflow – Abort generation and detection – Oversize and non-octet-aligned frame detection – CRC and alignment error generation TDM interface features: ● Six signals ● Duplex Tx/Rx communication ● Up to 16 Mbps pre Tx/Rx channel ● 256 time slots / frame(125 us) ● Supports any time-slot banding to any Tx/Rx channel ● Data sending/sampling time configurable ● Delay between bit 0 of TS0 and the SYNC signal configurable E1 interface main features: ● Six signals ● Duplex Tx/Rx communication ● Up to 2 Mbps pre Tx/Rx channel ● 32 time slot / frame(125 us) ● Supports any time-slot banding to any Tx/Rx channel ● Data sending/sampling time configurable ● Delay between the bit 0 of TS0 and the SYNC signal is configurable |
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