SPEAR1310 datasheet(45/57 Pages) STMICROELECTRONICS

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SPEAr1310

Security co-processor (C3)

Doc ID 17528 Rev 4

45/57

Security co-processor (C3)

C3 is a multipurpose, instruction driven, programmable DMA-based co-processor. It is

configured to accelerate cryptographic and network security functions.

30.1

Main features

●

AMBA AHB 2.0 master and slave interfaces

●

Scatter and gather DMA engine (implemented only by MPCM channel)

●

Instruction dispatchers

–

ID0 and ID1 available

–

ID2 and ID3 empty

●

Internal RAM: 4Kx32

●

Coupling/Chaining: 2 paths

The hardware accelerator crypto algorithms available in SPEAr1310 have the following

channels supported by mentioned operations:

●

Channel 0: Move channel

–

ID: 0x00001020

–

Supported operations: copy, AND, OR, XOR

–

Chained mode: either master or slave

–

Cascaded mode: both master and slave

–

Input FIFO: 8x32 bits

–

Output FIFO: 8x32 bits

●

Channel 1: Data encryption standard (DES and TripleDES)

–

ID: 0x00002001

–

Supported algorithms: DES (56-bit keys, ECB and CBC encryption/decryption, no

parity check) and TripleDES (168-bit keys, ECB and CBC encryption/decryption,

EncDecEnc)

–

Input FIFO: 16x32 bits

–

Output FIFO: 16x32 bits

●

Channel 2: MPCM for the advanced encryption standard (AES)

–

ID: 0x0000E000

–

Supported algorithms: AES (128-, 192-, 256-bit keys, ECB and CBC

encryption/decryption, with programmable operation modes to support almost all

possible modes, including Counter and XTS mode)

–

Memory for modes of operation: 512 words of 62 bits each

–

Input FIFO: 16x32 bits

–

Output FIFO: 16x32 bits

–

Read scatter/gather list: 4x32 bits

–

Write scatter/gather list: 4x32 bits

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