HT66F016 datasheet(40/116 Pages) HOLTEK

40 / 116 page

HT66F016/HT66F017/HT68F016/HT68F017

Rev. 1.00

May 14, 2012

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the in-

ternal clock, fS, which is in turn supplied by the LIRC os-

cillator. The LIRC internal oscillator has an approximate

period of 32 kHz at a supply voltage of 5V. However, it

should be noted that this specified internal clock period

can vary with VDD, temperature and process variations.

The Watchdog Timer source clock is then subdivided by

a ratio of 2

8 to 218 to give longer timeouts, the actual

value being chosen using the WS2~WS0 bits in the

WDTC register.

Watchdog Timer Control Register

A single register, WDTC, controls the required timeout

period as well as the enable/disable operation. This reg-

ister together with several configuration options control

the overall operation of the Watchdog Timer.

Watchdog Timer Operation

The Watchdog Timer operates by providing a device re-

set when its timer overflows. This means that in the ap-

plication program and during normal operation the user

has to strategically clear the Watchdog Timer before it

overflows to prevent the Watchdog Timer from execut-

ing a reset. This is done using the clear watchdog in-

structions. If the program malfunctions for whatever

reason, jumps to an unknown location, or enters an end-

less loop, these clear instructions will not be executed in

the correct manner, in which case the Watchdog Timer

will overflow and reset the device. Some of the Watch-

dog Timer options, such as always on select and clear

instruction type are selected using configuration op-

tions. With regard to the Watchdog Timer enable/dis-

able function, there are also five bits, WE4~WE0, in the

WDTC register to offer additional enable/disable and re-

set control of the Watchdog Timer. If the WDT configura-

tion option is determined that the WDT function is

always enabled, the WE4~WE0 bits still have effects on

the WDT function. When the WE4~WE0 bits value is

equal to 01010B or 10101B, the WDT function is en-

abled. However, if the WE4~WE0 bits are changed to

any other values except 01010B and 10101B, which is

caused by the environmental noise or software setting,

it will reset the microcontroller after 2~3 LIRC clock cy-

cles. If the WDT configuration option is determined that

the WDT function is controlled by the WDT control regis-

ter, the WE4~WE0 values can determine which mode

the WDT operates in. The WDT function will be disabled

when the WE4~WE0 bits are set to a value of 10101B.

The WDT function will be enabled if the WE4~WE0 bits

value is equal to 01010B. If the WE4~WE0 bits are set

to any other values by the environmental noise or soft-

ware setting, except 01010B and 10101B, it will reset

the device after 2~3 LIRC clock cycles. After power on

these bits will have the value of 01010B.

Watchdog Timer Enable/Disable Control

WDT Configura-

tion Option

WE4~WE0 Bits

WDT

Function

Always Enable

01010B or 10101B

Enable

Any other value

Reset MCU

Controlled by WDT

Control Register

10101B

Disable

01010B

Enable

Any other value

Reset MCU

Under normal program operation, a Watchdog Timer

time-out will initialise a device reset and set the status

bit TO. However, if the system is in the SLEEP or IDLE

Mode, when a Watchdog Timer time-out occurs, the TO

bit in the status register will be set and only the Program

Counter and Stack Pointer will be reset. Three methods

can be adopted to clear the contents of the Watchdog

Timer. The first is a WDT reset, which means a certain

value except 01010B and 10101B written into the

WE4~WE0 bit filed, the second is using the Watchdog

Timer software clear instructions and the third is via a

HALT instruction.

There is only one method of using software instruction

to clear the Watchdog Timer. That is to use the single

²CLR WDT² instruction to clear the WDT.

8 - s t a g e D i v i d e r

f S

W D T T i m e - o u t

( 2 8 / f S ~ 2 1 8 / f S )

f S / 2 8

W D T P r e s c a l e r

8 - t o - 1 M U X

C L R W D T

C L R

W S 2 ~ W S 0

( f S / 2 8 ~ f S / 2 1 8 )

L I R C

f L I R C

W E 4 ~ W E 0 b i t s

R e s e t M C U

W D T C R e g i s t e r

Watchdog Timer

HT66F016 датащи(PDF) 40 Page - Holtek Semiconductor Inc

HT66F016 датащи(HTML) 40 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL