HT66F016 datasheet(57/116 Pages) HOLTEK

57 / 116 page

HT66F016/HT66F017/HT68F016/HT68F017

Rev. 1.00

May 14, 2012

Bit 2

T0POL: TP0 output polarity control

0: non-invert

1: invert

This bit controls the polarity of the TP0 output pin. When the bit is set high the TM

output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the

Timer/Counter Mode.

Bit 1

T0DPX: TM0 PWM period/duty control

0: CCRP - period; CCRA - duty

1: CCRP - duty; CCRA - period

This bit, determines which of the CCRA and CCRP registers are used for period and duty

control of the PWM waveform.

Bit 0

T0CCLR: select TM0 counter clear condition

0: TM0 Comparatror P match

1: TM0 Comparatror A match

This bit is used to select the method which clears the counter. Remember that the Compact TM

contains two comparators, Comparator A and Comparator P, either of which can be selected to

clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a

compare match occurs from the Comparator A. When the bit is low, the counter will be cleared

when a compare match occurs from the Comparator P or with a counter overflow. A counter

overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.

The T0CCLR bit is not used in the PWM Mode.

· TM0RP Register

Bit

76543210

Name

T0RP7

T0RP6

T0RP5

T0RP4

T0RP3

T0RP2

T0RP1

T0RP0

R/W

POR

00000000

Bit 7~0

T0RP7~T0RP0: TM0 CCRP register bit 7~bit 0, compared with the TM0 counter bit 15~bit 8

Comparator P match period =

0: 65536 TM0 clocks

1~255: (1~255)

´ 256 TM0 clocks

These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then

compared with the internal counter's highest eight bits. The result of this comparison can be

selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to

zero ensures that a compare match with the CCRP values will reset the internal counter.

As the CCRP bits are only compared with the highest eight counter bits, the compare values

exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to

overflow at its maximum value.

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